Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Saturday, April 22, 2023 8:16 PM
>
> On Sat, Apr 22, 2023 at 04:39:56PM +0530, Manivannan Sadhasivam wrote:
> > On Tue, Apr 18, 2023 at 09:23:47PM +0900, Yoshihiro Shimoda wrote:
> > > To add more arguments to the dw_pcie_prog_ep_outbound_atu() in
> > > the future, introduce struct dw_pcie_outbound_atu. No behavior changes.
> > >
> >
> > Why are you limiting this struct within DWC core and not exposing to client
> > drivers?
>
> Sry, not client drivers but with the dw_pcie_ep_outbound_atu() API.
Thank you for your comments! I'll modify this patch on v13.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> >
> > - Mani
> >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > > ---
> > > drivers/pci/controller/dwc/pcie-designware.c | 66 ++++++++++++--------
> > > drivers/pci/controller/dwc/pcie-designware.h | 9 +++
> > > 2 files changed, 48 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > index ede166645289..92bee9d5180d 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > @@ -464,56 +464,55 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> > > return val | PCIE_ATU_TD;
> > > }
> > >
> > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > - int index, int type, u64 cpu_addr,
> > > - u64 pci_addr, u64 size)
> > > +static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > + struct dw_pcie_outbound_atu *atu)
> > > {
> > > u32 retries, val;
> > > u64 limit_addr;
> > >
> > > if (pci->ops && pci->ops->cpu_addr_fixup)
> > > - cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
> > > + atu->cpu_addr = pci->ops->cpu_addr_fixup(pci, atu->cpu_addr);
> > >
> > > - limit_addr = cpu_addr + size - 1;
> > > + limit_addr = atu->cpu_addr + atu->size - 1;
> > >
> > > - if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> > > - !IS_ALIGNED(cpu_addr, pci->region_align) ||
> > > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> > > + if ((limit_addr & ~pci->region_limit) != (atu->cpu_addr & ~pci->region_limit) ||
> > > + !IS_ALIGNED(atu->cpu_addr, pci->region_align) ||
> > > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> > > return -EINVAL;
> > > }
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> > > - lower_32_bits(cpu_addr));
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> > > - upper_32_bits(cpu_addr));
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> > > + lower_32_bits(atu->cpu_addr));
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> > > + upper_32_bits(atu->cpu_addr));
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> > > lower_32_bits(limit_addr));
> > > if (dw_pcie_ver_is_ge(pci, 460A))
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> > > upper_32_bits(limit_addr));
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> > > - lower_32_bits(pci_addr));
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> > > - upper_32_bits(pci_addr));
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> > > + lower_32_bits(atu->pci_addr));
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > + upper_32_bits(atu->pci_addr));
> > >
> > > - val = type | PCIE_ATU_FUNC_NUM(func_no);
> > > - if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > + if (upper_32_bits(limit_addr) > upper_32_bits(atu->cpu_addr) &&
> > > dw_pcie_ver_is_ge(pci, 460A))
> > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > if (dw_pcie_ver_is(pci, 490A))
> > > val = dw_pcie_enable_ecrc(val);
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > >
> > > /*
> > > * Make sure ATU enable takes effect before any subsequent config
> > > * and I/O accesses.
> > > */
> > > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> > > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> > > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> > > if (val & PCIE_ATU_ENABLE)
> > > return 0;
> > >
> > > @@ -528,16 +527,29 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > u64 cpu_addr, u64 pci_addr, u64 size)
> > > {
> > > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> > > - cpu_addr, pci_addr, size);
> > > + struct dw_pcie_outbound_atu atu = { 0 };
> > > +
> > > + atu.index = index;
> > > + atu.type = type;
> > > + atu.cpu_addr = cpu_addr;
> > > + atu.pci_addr = pci_addr;
> > > + atu.size = size;
> > > + return __dw_pcie_prog_outbound_atu(pci, &atu);
> > > }
> > >
> > > int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > int type, u64 cpu_addr, u64 pci_addr,
> > > u64 size)
> > > {
> > > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> > > - cpu_addr, pci_addr, size);
> > > + struct dw_pcie_outbound_atu atu = { 0 };
> > > +
> > > + atu.func_no = func_no;
> > > + atu.index = index;
> > > + atu.type = type;
> > > + atu.cpu_addr = cpu_addr;
> > > + atu.pci_addr = pci_addr;
> > > + atu.size = size;
> > > + return __dw_pcie_prog_outbound_atu(pci, &atu);
> > > }
> > >
> > > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > index 9acf6c40d252..c6556ee24836 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > @@ -291,6 +291,15 @@ enum dw_pcie_core_rst {
> > > DW_PCIE_NUM_CORE_RSTS
> > > };
> > >
> > > +struct dw_pcie_outbound_atu {
> > > + u64 cpu_addr;
> > > + u64 pci_addr;
> > > + u64 size;
> > > + int index;
> > > + int type;
> > > + u8 func_no;
> > > +};
> > > +
> > > struct dw_pcie_host_ops {
> > > int (*host_init)(struct dw_pcie_rp *pp);
> > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > --
> > > 2.25.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
