Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
the global register start address
The RTK DHC SoCs were designed the global register address offset at
0x8100. The default address offset is constant at DWC3_GLOBALS_REGS_START
(0xc100). Therefore, add the property of device-tree to adjust this
address offset.
Signed-off-by: Stanley Chang <stanley_chang@xxxxxxxxxxx>
---
v2 to v3 change:
1. Fix the dtschema validation error.
v1 to v2 change:
1. Change the name of the property "snps,global-regs-starting-offset".
2. Adjust the format of comment.
3. Add initial value of the global_regs_starting_offset
4. Remove the log of dev_info.
---
Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index be36956af53b..4f83fa8cb6cb 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -359,6 +359,14 @@ properties:
items:
enum: [1, 4, 8, 16, 32, 64, 128, 256]
+ snps,global-regs-starting-offset:
+ description:
+ value for remapping global register start address. For some dwc3
+ controller, the dwc3 global register start address is not at
+ default DWC3_GLOBALS_REGS_START (0xc100). This property is added to
+ adjust the address.
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+
port:
$ref: /schemas/graph.yaml#/properties/port
description:
--
2.34.1
