The StarFive JH7110 SoC has four RISC-V cores,
and it supports up to 4 cpu frequency loads.
This patchset adds the compatible strings into the allowlist
for supporting the generic cpufreq driver on JH7110 SoC.
Also, it enables the axp15060 pmic for the cpu power source.
The series has been tested on the VisionFive 2 boards which
are equipped with JH7110 SoC and axp15060 pmic.
This patchset is based on v6.3-rc4 with these patches applied:
[1] ("Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC")
https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@xxxxxxxxxxxxxxxx/
[2] ("Add X-Powers AXP15060 PMIC support")
https://lore.kernel.org/all/TY3P286MB2611A814E580C96DC6F187B798969@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/
Changes since v2:
- Fix the new blank line at EOF issue in dtsi.
Changes since v1:
- Fix dts node naming issues.
- Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
- Follow the alphabetical order to place the cpufreq dt allowlist.
---
v1: https://lore.kernel.org/all/20230411083257.16155-1-mason.huo@xxxxxxxxxxxxxxxx/
v2: https://lore.kernel.org/lkml/20230417063942.3141-1-mason.huo@xxxxxxxxxxxxxxxx/
Mason Huo (3):
riscv: dts: starfive: Enable axp15060 pmic for cpufreq
cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
riscv: dts: starfive: Add cpu scaling for JH7110 SoC
.../jh7110-starfive-visionfive-2.dtsi | 30 +++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
3 files changed, 65 insertions(+)
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
--
2.39.2
