Assign top_a1sys_hp clock to 26M, and add apll1_d4 to clocks for switching
the parent of top_a1sys_hp dynamically
On the other hand, "mediatek,infracfg" is included for bus protection.
Signed-off-by: Trevor Wu <trevor.wu@xxxxxxxxxxxx>
---
.../bindings/sound/mediatek,mt8188-afe.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
index 82ccb32f08f2..03301d5082f3 100644
--- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
@@ -29,6 +29,10 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek topckgen controller
+ mediatek,infracfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the mediatek infracfg controller
+
power-domains:
maxItems: 1
@@ -37,6 +41,7 @@ properties:
- description: 26M clock
- description: audio pll1 clock
- description: audio pll2 clock
+ - description: audio pll1 divide 4
- description: clock divider for i2si1_mck
- description: clock divider for i2si2_mck
- description: clock divider for i2so1_mck
@@ -58,6 +63,7 @@ properties:
- const: clk26m
- const: apll1
- const: apll2
+ - const: apll1_d4
- const: apll12_div0
- const: apll12_div1
- const: apll12_div2
@@ -74,6 +80,12 @@ properties:
- const: i2si2_m_sel
- const: adsp_audio_26m
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
mediatek,etdm-in1-cowork-source:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@@ -147,6 +159,8 @@ required:
- power-domains
- clocks
- clock-names
+ - assigned-clocks
+ - assigned-clock-parents
additionalProperties: false
@@ -170,6 +184,7 @@ examples:
clocks = <&clk26m>,
<&apmixedsys 9>, //CLK_APMIXED_APLL1
<&apmixedsys 10>, //CLK_APMIXED_APLL2
+ <&topckgen 136>, //CLK_TOP_APLL1_D4
<&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
<&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
<&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
@@ -188,6 +203,7 @@ examples:
clock-names = "clk26m",
"apll1",
"apll2",
+ "apll1_d4",
"apll12_div0",
"apll12_div1",
"apll12_div2",
@@ -203,6 +219,8 @@ examples:
"i2si1_m_sel",
"i2si2_m_sel",
"adsp_audio_26m";
+ assigned-clocks = <&topckgen 83>; //CLK_TOP_A1SYS_HP
+ assigned-clock-parents = <&clk26m>;
};
...
--
2.18.0
