Thanks Raghavendra
On 13/04/23 10:53, Vignesh Raghavendra wrote:
Hi Udit,
On 13/04/23 10:45, Udit Kumar wrote:
Hi Nishanth,
On 13/04/23 01:26, Nishanth Menon wrote:
On 23:06-20230412, Udit Kumar wrote:
[..]
Are you saying that j721s2 is incapable of l3 cache? say some level 1
errata?
No
or is it because, the chip is really capable of l3 cache and we are
really setting it to 0?
https://git.ti.com/cgit/k3-image-gen/k3-image-gen/tree/soc/j721s2/evm/board-cfg.c#n71
This is because, l3 cache size is set to zero.
unless the chip has an errata, you are supposed to fix it up based on
configuration by using the API and this patch is a NAK
https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-query-msmc
ok
U-Boot already does this. See fdt_fixup_msmc_ram() at board/ti/j721s2/evm.c
tifs-sram fixup probably is still needed and possible bug in the original patch?
Let me fix in u-boot
Regards
Udit
