From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Hookup the Andes AX45MP non-coherent handling by updating the
ALT_CMO_OP() macro which will be used by dma-noncoherent.c for
non-coherent platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
v7->v8
* New patch
---
arch/riscv/include/asm/cacheflush.h | 9 ++++++++
arch/riscv/include/asm/errata_list.h | 33 ++++++++++++++++++++++------
2 files changed, 35 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index 8091b8bf4883..a8503cc04fdb 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -59,6 +59,15 @@ void riscv_noncoherent_supported(void);
static inline void riscv_noncoherent_supported(void) {}
#endif
+#ifdef CONFIG_AX45MP_L2_CACHE
+extern asmlinkage void ax45mp_dma_cache_wback_inv(void *vaddr, unsigned long size);
+extern asmlinkage void ax45mp_dma_cache_wback(void *vaddr, unsigned long size);
+extern asmlinkage void ax45mp_dma_cache_inv(void *vaddr, unsigned long size);
+#else
+static inline void ax45mp_dma_cache_wback_inv(void *vaddr, unsigned long size) {}
+static inline void ax45mp_dma_cache_wback(void *vaddr, unsigned long size) {}
+static inline void ax45mp_dma_cache_inv(void *vaddr, unsigned long size) {}
+#endif
/*
* Bits in sys_riscv_flush_icache()'s flags argument.
*/
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index e2ecd01bfac7..8e9811c14ba3 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -122,9 +122,13 @@ asm volatile(ALTERNATIVE( \
#define THEAD_flush_A0 ".long 0x0275000b"
#define THEAD_SYNC_S ".long 0x0190000b"
+#define ANDESTECH_AX45MP_clean "call ax45mp_dma_cache_wback"
+#define ANDESTECH_AX45MP_inval "call ax45mp_dma_cache_inv"
+#define ANDESTECH_AX45MP_flush "call ax45mp_dma_cache_wback_inv"
+
#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
-asm volatile(ALTERNATIVE_2( \
- __nops(6), \
+asm volatile(ALTERNATIVE_3( \
+ __nops(11), \
"mv a0, %1\n\t" \
"j 2f\n\t" \
"3:\n\t" \
@@ -132,7 +136,7 @@ asm volatile(ALTERNATIVE_2( \
"add a0, a0, %0\n\t" \
"2:\n\t" \
"bltu a0, %2, 3b\n\t" \
- "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
+ __nops(6), 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
"mv a0, %1\n\t" \
"j 2f\n\t" \
"3:\n\t" \
@@ -140,12 +144,27 @@ asm volatile(ALTERNATIVE_2( \
"add a0, a0, %0\n\t" \
"2:\n\t" \
"bltu a0, %2, 3b\n\t" \
- THEAD_SYNC_S, THEAD_VENDOR_ID, \
- ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
+ THEAD_SYNC_S "\n\t" \
+ __nops(5), THEAD_VENDOR_ID, \
+ ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO, \
+ "addi sp,sp,-16\n\t" \
+ "sd s0,0(sp)\n\t" \
+ "sd ra,8(sp)\n\t" \
+ "addi s0,sp,16\n\t" \
+ "mv a1,%4\n\t" \
+ "mv a0,%3\n\t" \
+ ANDESTECH_AX45MP_##_op "\n\t" \
+ "ld ra,8(sp)\n\t" \
+ "ld s0,0(sp)\n\t" \
+ "addi sp,sp,16\n\t", \
+ ANDESTECH_VENDOR_ID, ERRATA_ANDESTECH_NO_IOCP, \
+ CONFIG_ERRATA_ANDES) \
: : "r"(_cachesize), \
"r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
- "r"((unsigned long)(_start) + (_size)) \
- : "a0")
+ "r"((unsigned long)(_start) + (_size)), \
+ "r"((void *)(_start)), \
+ "r"((unsigned long)(_size)) \
+ : "a0", "a1")
#define THEAD_C9XX_RV_IRQ_PMU 17
#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
--
2.25.1
