> Subject: Re: [PATCH v4 4/4] crypto: starfive - Add hash and HMAC support > > On Mon, Apr 10, 2023 at 04:43:37PM +0800, Jia Jie Ho wrote: > > > > The hardware requires user to set a 'final' bit after data transfer completed. > > This completion is to wait for the interrupt signal from device that > > the final digest has been populated to the read registers. > > > > I'll do the finalize_request call directly in the next version. > > Instead of the IRQ performing a completion, it could instead schedule a tasklet > and do the callback directly from the tasklet. > > Actually, the ordering between the IRQ and DMA callback is a bit confusing. > Which one is supposed to occur first and how does it interact with the other > event? > The sequence of event would be: 1. Wait for DMA transfer to complete. 2. Set bit in device CSR to indicate final block has been transferred. 3. Device will send IRQ once result is ready. 4. Read out final digest value from device. Thanks, Jia Jie
