Hi Florian, On 23-04-05, Florian Fainelli wrote: > Hi Marco, > > On 4/5/2023 2:26 AM, Marco Felsch wrote: > > The current phy reset handling is broken in a way that it needs > > pre-running firmware to setup the phy initially. Since the very first > > step is to readout the PHYID1/2 registers before doing anything else. > > > > The whole dection logic will fall apart if the pre-running firmware > > don't setup the phy accordingly or the kernel boot resets GPIOs states > > or disables clocks. In such cases the PHYID1/2 read access will fail and > > so the whole detection will fail. > > PHY reset is a bit too broad and should need some clarifications between: > > - external reset to the PHY whereby a hardware pin on the PHY IC may be used > > - internal reset to the PHY whereby we call into the PHY driver soft_reset > function to have the PHY software reset itself > > You are changing the way the former happens, not the latter, at least not > changing the latter intentionally if at all. Yes. > This is important because your cover letter will be in the merge commit in > the networking tree. Ah okay, I didn't know that. I will adapt the cover letter accordingly. > Will do a more thorough review on a patch by patch basis. Thanks. Thanks a lot, looking forward to it. Regards, Marco
