Many divider hardware use a (n+1) scheme to prevent a zero divider.
Signed-off-by: Alban Bedel <albeu@xxxxxxx>
---
drivers/clk/clk-fractional-divider.c | 4 ++++
include/linux/clk-provider.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index b562281..bcee7f7d3 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -35,6 +35,8 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
+ if (fd->flags & CLK_FRACTIONAL_DIVIDER_DIVISOR_PLUS_ONE)
+ n += 1;
ret = (u64)parent_rate * m;
do_div(ret, n);
@@ -74,6 +76,8 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
div = gcd(parent_rate, rate);
m = rate / div;
n = parent_rate / div;
+ if (fd->flags & CLK_FRACTIONAL_DIVIDER_DIVISOR_PLUS_ONE)
+ n -= 1;
if (fd->lock)
spin_lock_irqsave(fd->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 29ea77a..00013b1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -463,6 +463,7 @@ struct clk_fractional_divider {
};
#define CLK_FRACTIONAL_DIVIDER_READ_ONLY BIT(0)
+#define CLK_FRACTIONAL_DIVIDER_DIVISOR_PLUS_ONE BIT(1)
extern const struct clk_ops clk_fractional_divider_ops;
extern const struct clk_ops clk_fractional_divider_ro_ops;
--
2.0.0
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