Il 31/03/23 10:49, Boris Brezillon ha scritto:
On Fri, 31 Mar 2023 10:11:07 +0200
AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
wrote:
Il 23/03/23 10:08, AngeloGioacchino Del Regno ha scritto:
Some SoCs implementing ARM Mali GPUs are subject to speed binning:
this means that some versions of the same SoC model may need to be
limited to a slower frequency compared to the other:
this is being addressed by reading nvmem (usually, an eFuse array)
containing a number that identifies the speed binning of the chip,
which is usually related to silicon quality.
To address such situation, add basic support for reading the
speed-bin through nvmem, as to make it possible to specify the
supported hardware in the OPP table for GPUs.
This commit also keeps compatibility with any platform that does
not specify (and does not even support) speed-binning.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
Hello maintainers,
I've seen that this got archived in the dri-devel patchwork; because of that and
only that, I'm sending this ping to get this patch reviewed.
Looks good to me. If you can get a DT maintainer to review the binding
(Rob?), I'd be happy to queue the series to drm-misc-next.
The binding was acked by Krzysztof already... so, just to be sure:
Krzysztof, can the binding [1] get picked?
Cheers,
Angelo
[1]:
https://lore.kernel.org/all/20230323090822.61766-2-angelogioacchino.delregno@xxxxxxxxxxxxx/
