[AMD Official Use Only - General]
> -----Original Message-----
> From: Borislav Petkov <bp@xxxxxxxxx>
> Sent: Saturday, March 25, 2023 12:19 AM
> To: Datta, Shubhrajyoti <shubhrajyoti.datta@xxxxxxx>
> Cc: linux-edac@xxxxxxxxxxxxxxx; git (AMD-Xilinx) <git@xxxxxxx>;
> michal.simek@xxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> krzysztof.kozlowski@xxxxxxxxxx; robh+dt@xxxxxxxxxx; mchehab@xxxxxxxxxx;
> tony.luck@xxxxxxxxx
> Subject: Re: [PATCH v3 2/2] edac: xilinx: Added EDAC support for Xilinx DDR
> controller
>
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>
> > <snip>
> > > > + ulong err_addr = 0;
> > > > + u32 index;
> > > > +
> > > > + for (index = 0; index < XDDR_MAX_ROW_CNT; index++) {
> > > > + err_addr |= (pinf.row & BIT(0)) << priv->row_bit[index];
> > > > + pinf.row >>= 1;
> > > > + }
<snip>
> >
> > I did not understand this one . The loop are running for different indixes.
>
> Let's take the first one. Isn't what you're doing equivalent to simply:
>
> err_addr = pinf.row & GENMASK_ULL(0, XDDR_MAX_ROW_CNT);
> err_addr <<= XDDR_MAX_ROW_CNT;
>
> ?
>
> You basically stick in the error address each segment one after the other...
>
> err_addr = [XDDR_MAX_ROW_CNT ... XDDR_MAX_COL_CNT ...
> XDDR_MAX_BANK_CNT .. ]
>
> and so on?
Basically we get the row_bit position from the adec registers and that is stored in
priv->row_bit[index];
we then get the bit and write it to the position specified by the row_bit[index];
this bit is dependent on the design and we read from the ADEC registers.
>
> Thx.
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
