On Fri, Mar 17, 2023 at 07:54:41AM -0700, Lars-Peter Clausen wrote: > The maximum transfer length is a synthesis configuration parameters of the > Cadence I2C IP. Different SoCs might use different values for these > parameters. > > Currently the driver has the maximum transfer length hardcoded to 255. > Trying to use the driver with an IP instance that uses smaller values for > these will work for short transfers. But longer transfers will fail. > > The maximum transfer length can easily be detected at runtime since the > unused MSBs of the transfer length register are hardwired to 0. Writing > 0xff and then reading back the value will give the maximum transfer length. > > These changes have been tested with > 1) The Xilinx MPSoC for which this driver was originally written which > has the previous hardcoded settings of 16 and 255. > 2) Another instance of the Cadence I2C IP with FIFO depth of 8 and > maximum transfer length of 16. > > Without these changes the latter would fail for I2C transfers longer than > 16. With the updated driver both work fine even for longer transfers. > > Note that the IP core and driver support chaining multiple transfers into a > single longer transfer using the HOLD bit. So the maximum transfer size is > not the limit for the length of the I2C transfer, but the limit for how > much data can be transferred without having to reprogram the control > registers. > > Signed-off-by: Lars-Peter Clausen <lars@xxxxxxxxxx> Applied to for-next, thanks!
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