Re: [Patch v4 10/10] PCI: tegra194: add interconnect support in Tegra234

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On 29/03/23 22:29, Bjorn Helgaas wrote:
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On Wed, Mar 29, 2023 at 02:44:34PM +0530, Sumit Gupta wrote:
On 28/03/23 23:23, Bjorn Helgaas wrote:
+static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie)
+{
+     struct dw_pcie *pci = &pcie->pci;
+     u32 val, speed, width;
+
+     val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
+
+     speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
+     width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
+
+     val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) / BITS_PER_BYTE);
+
+     if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0))
+             dev_err(pcie->dev, "can't set bw[%u]\n", val);
+
+     clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);

Array bounds violation; PCI_EXP_LNKSTA_CLS is 0x000f, so possible
speed (CLS) values are 0..0xf and "speed - 1" values are -1..0xe.

pcie_gen_freq[] is of size 4 (valid indices 0..3).

I see that you're just *moving* this code, but might as well fix it.

Thank you for the review.
Will include the below change in the same patch. Please let me know if any
issue.

  -       clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
  +       if (speed && (speed <= ARRAY_SIZE(pcie_gen_freq)))
  +               clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
  +       else
  +               clk_set_rate(pcie->core_clk, pcie_gen_freq[0]);

I didn't notice that speed is a u32, so -1 is not a possible value.
Also, it's used earlier for PCIE_SPEED2MBS_ENC(), so you could do
something like this:

   speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val) - 1;
   if (speed >= ARRAY_SIZE(pcie_gen_freq))
     speed = 0;

   val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) /
         BITS_PER_BYTE);
   ...
   clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);

I tried this change but PCIE_SPEED2MBS_ENC gives zero when speed value is one. The speed value ranges from "1 to 4" and for value "1", pcie_link_speed[speed] gives '0xff'.

 const unsigned char pcie_link_speed[] = {
         PCI_SPEED_UNKNOWN,              /* 0 */

The below change works fine. Please share if its OK to add it in patch.

  speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
  if (!speed || speed >= ARRAY_SIZE(pcie_gen_freq))
          speed = 1;

val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) / BITS_PER_BYTE);

  if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0))
          dev_err(pcie->dev, "can't set bw[%u]\n", val);

  clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);


Thank you,
Sumit Gupta



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