Hi, Nicolas! I just compiled tested this with sama5_defconfig and at91_dt_defconfig. Would you please do a simnple test on your side to make sure everything is in place? A test on a single board would suffice (maybe sama5d27-wlsom1-ek?): #!/bin/sh dd if=/dev/urandom of=./qspi_test bs=1M count=6 mtd_debug write /dev/mtd5 0 6291456 qspi_test mtd_debug erase /dev/mtd5 0 6291456 mtd_debug read /dev/mtd5 0 6291456 qspi_read hexdump qspi_read mtd_debug write /dev/mtd5 0 6291456 qspi_test mtd_debug read /dev/mtd5 0 6291456 qspi_read sha1sum qspi_test qspi_read Cheers, ta Changes in v2: update value of spi-cs-setup-ns as it was changed to u32 since the first proposal. v1 at: https://lore.kernel.org/linux-mtd/20221117105249.115649-1-tudor.ambarus@xxxxxxxxxxxxx/ --- SPI NOR flashes have specific cs-setup time requirements without which they can't work at frequencies close to their maximum supported frequency, as they miss the first bits of the instruction command. Unrecognized commands are ignored, thus the flash will be unresponsive. Introduce the spi-cs-setup-ns property to allow spi devices to specify their cs setup time. Tudor Ambarus (4): ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency arch/arm/boot/dts/at91-sam9x60ek.dts | 3 ++- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 3 ++- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) -- 2.40.0.348.gf938b09366-goog
