On 3/27/2023 1:59 PM, Apurva Nandan wrote:
> Add support for OSPI flash connected to OSPI0 instance through FSS.
> Also enumerate OSPI1 instance in MCU DTSI.
>
> Signed-off-by: Apurva Nandan <a-nandan@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 44 +++++++++++++++++++
> .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 43 ++++++++++++++++++
> 2 files changed, 87 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index 8cd4a7ecc121..7480f37e89e8 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -138,6 +138,24 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
> J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
> >;
> };
> +
> + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
> + pinctrl-single,pins = <
> + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
> + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
> + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
> + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
> + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
> + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
> + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
> + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
> + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
> + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
> + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
> + J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */
> + J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */
> + >;
> + };
> };
>
> &main_uart8 {
> @@ -146,6 +164,32 @@ &main_uart8 {
> pinctrl-0 = <&main_uart8_pins_default>;
> };
>
> +&fss {
> + status = "okay";
> +};
> +
> +&ospi0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> + spi-tx-bus-width = <8>;
> + spi-rx-bus-width = <8>;
> + spi-max-frequency = <25000000>;
> + cdns,tshsl-ns = <60>;
> + cdns,tsd2d-ns = <60>;
> + cdns,tchsh-ns = <60>;
> + cdns,tslch-ns = <60>;
> + cdns,read-delay = <4>;
> + cdns,phy-mode;
Need binding doc
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +};
> +
> &main_i2c0 {
> status = "okay";
> pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> index 93952af618f6..b29b95a532f6 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> @@ -308,4 +308,47 @@ cpts@3d000 {
> ti,cpts-periodic-outputs = <2>;
> };
> };
> +
> + fss: syscon@47000000 {
> + compatible = "syscon", "simple-mfd";
NACK. Please run make dtbs_check and fix all the issues..
See whats being done for J721s2 [0] for example
[0] https://lore.kernel.org/linux-arm-kernel/20230309082940.31535-1-r-gunasekaran@xxxxxx/
> + reg = <0x00 0x47000000 0x00 0x100>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
Lets keep the FSS enabled as there is not board dependency
and disable individual SPI controllers
> +
> + ospi0: spi@47040000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47040000 0x00 0x100>,
> + <0x5 0x0000000 0x1 0x0000000>;
<0x05 0x0000000 0x01 0x0000000>;
> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 161 7>;
> + assigned-clocks = <&k3_clks 161 7>;
> + assigned-clock-parents = <&k3_clks 161 9>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + ospi1: spi@47050000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47050000 0x00 0x100>,
> + <0x7 0x0000000 0x1 0x0000000>;
<0x07 0x0000000 0x01 0x0000000>;
> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 162 7>;
> + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
> };
Regards
Vignesh
