From: Ondrej Jirman <megi@xxxxxx>
The phone's display is using a Hannstar LCD panel. Support it by adding a
panel DT node and all needed nodes (backlight, MIPI DSI, regulators, etc).
Signed-off-by: Ondrej Jirman <megi@xxxxxx>
Co-developed-by: Martijn Braam <martijn@xxxxxxxxx>
Co-developed-by: Kamil Trzciński <ayufan@xxxxxxxxx>
Signed-off-by: Javier Martinez Canillas <javierm@xxxxxxxxxx>
---
Changes in v2:
- Drop touchscreen node because used the wrong compatible (Ondrej Jirman).
- Fix assigned-clock-parents in vopb node (Ondrej Jirman).
- Add vopl and vopl nodes.
.../dts/rockchip/rk3399-pinephone-pro.dts | 111 ++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
index a0795a2b1cb1..5116f156d548 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
@@ -29,6 +29,12 @@ chosen {
stdout-path = "serial2:115200n8";
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 1000000 0>;
+ pwm-delay-us = <10000>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -102,6 +108,32 @@ wifi_pwrseq: sdio-wifi-pwrseq {
/* WL_REG_ON on module */
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
+
+ /* MIPI DSI panel 1.8v supply */
+ vcc1v8_lcd: vcc1v8-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc1v8_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_pwren1>;
+ };
+
+ /* MIPI DSI panel 2.8v supply */
+ vcc2v8_lcd: vcc2v8-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc2v8_lcd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&vcc3v3_sys>;
+ gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_pwren>;
+ };
};
&cpu_alert0 {
@@ -139,6 +171,11 @@ &emmc_phy {
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
@@ -362,6 +399,40 @@ &io_domains {
status = "okay";
};
+&mipi_dsi {
+ status = "okay";
+ clock-master;
+
+ ports {
+ mipi_out: port@1 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "hannstar,hsd060bhw4";
+ reg = <0>;
+ backlight = <&backlight>;
+ reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vcc2v8_lcd>; // 2v8
+ iovcc-supply = <&vcc1v8_lcd>; // 1v8
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_rst_l>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
&pmu_io_domains {
pmu1830-supply = <&vcc_1v8>;
status = "okay";
@@ -374,6 +445,20 @@ pwrbtn_pin: pwrbtn-pin {
};
};
+ dsi {
+ display_rst_l: display-rst-l {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ display_pwren: display-pwren {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ display_pwren1: display-pwren1 {
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -429,6 +514,10 @@ &sdio0 {
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
@@ -479,3 +568,25 @@ bluetooth {
&uart2 {
status = "okay";
};
+
+&vopb {
+ status = "okay";
+ assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
+ assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+ assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
+ assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
+};
+
+&vopl_mmu {
+ status = "okay";
+};
base-commit: da8e7da11e4ba758caf4c149cc8d8cd555aefe5f
--
2.39.2
