On 26/03/2023 20:40, Shane Francis wrote: > Some vendor uboot bootloaders use the target kernels DTB image to > determine the target clock speeds for some PLLs, currently this can cause > uboot to set the clock rate for gpll incorrectly on to cpll (breaking) > RGMII. Do not attach (thread) your patchsets to some other threads (unrelated or older versions). This buries them deep in the mailbox and might interfere with applying entire sets. > > This change starts the PLL clock definitions from 1 to correct this > miss-match > > This could be handled by uboot bu updating mappings in that code base > however not all devices will have a replaceable uboot (in cases such as > when a secure boot chain is implemented) > > Signed-off-by: Shane Francis <bigbeeshane@xxxxxxxxx> > --- > .../dt-bindings/clock/rockchip,rk3588-cru.h | 1442 ++++++++--------- > 1 file changed, 721 insertions(+), 721 deletions(-) > > diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h > index b5616bca7b44..d63b07d054b7 100644 > --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h > +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h We did not finish discussion yet, so sending new version 50 minutes after your last reply does not give me chance to respond. Best regards, Krzysztof
