On 26/03/2023 01:15, Shane Francis wrote: > Some vendor uboot bootloaders use the target kernels > DTB image to determine the target clock speeds for > some PLLs, currently this can cause uboot to set the > clock rate for gpll incorrectly on to cpll (breaking) Please wrap commit message according to Linux coding style / submission process (neither too early nor over the limit): https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586 > RGMII. > > This change starts the PLL clock definitions from 1 > to correct this miss-match Unfortunately the reason is not good enough for ABI break. Replace vendor boot uboots with open-source one or just correct them (it's still U-Boot so even for vendor one you have the source). > > Signed-off-by: Shane Francis <bigbeeshane@xxxxxxxxx> > --- > .../dt-bindings/clock/rockchip,rk3588-cru.h | 1442 ++++++++--------- > 1 file changed, 721 insertions(+), 721 deletions(-) > > diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h > index b5616bca7b44..d63b07d054b7 100644 > --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h > +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h > @@ -12,727 +12,727 @@ > > /* cru-clocks indices */ > > -#define PLL_B0PLL 0 Best regards, Krzysztof
