On Fri, Mar 24, 2023 at 02:46:51PM +0800, Hal Feng wrote: > The S7 core has no L1 data cache and MMU, so delete some > related properties. > > Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> > --- > > Hi, Conor, > > This is a correction for the S7 entry. Again going off the latest version of the u74-mc core complex, this looks to be correct, thanks. I need to go read the Emil email from earier today, but I've provisionally gone and put this on the riscv-jh7100_initial_dts branch with a Fixes: tag. Thanks, Conor. > This patch depends on patch [1]. > > [1] https://lore.kernel.org/all/20230320103750.60295-20-hal.feng@xxxxxxxxxxxxxxxx/ > > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 --------- > 1 file changed, 9 deletions(-) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index d484ecdf93f7..4c5fdb905da8 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -20,21 +20,12 @@ cpus { > S7_0: cpu@0 { > compatible = "sifive,s7", "riscv"; > reg = <0>; > - d-cache-block-size = <64>; > - d-cache-sets = <64>; > - d-cache-size = <8192>; > - d-tlb-sets = <1>; > - d-tlb-size = <40>; > device_type = "cpu"; > i-cache-block-size = <64>; > i-cache-sets = <64>; > i-cache-size = <16384>; > - i-tlb-sets = <1>; > - i-tlb-size = <40>; > - mmu-type = "riscv,sv39"; > next-level-cache = <&ccache>; > riscv,isa = "rv64imac_zba_zbb"; > - tlb-split; > status = "disabled"; > > cpu0_intc: interrupt-controller { > -- > 2.38.1 >
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