On 3/21/23 16:23, Stephen Boyd wrote:
Quoting Florian Fainelli (2023-03-21 16:09:54)
On 3/21/23 16:06, Stephen Boyd wrote:
Quoting Florian Fainelli (2023-03-21 16:00:29)
These SoCs are big-endian, require native endian register access and
have no posted writes within their bus logic (UBUS) and require no
barriers, hence the use of __raw_readl() and __raw_writel() is adequate.
Use ioread32be() then?
BCM63xx drivers tend to use __raw_{read,write}l for consistency and to
make it clear that no barriers, no endian swapping is necessary, I would
prefer to remain consistent with that convention.
Ok.
Is the clk device big-endian? Or the CPU is big-endian? SoC being
big-endian sounds like the devices in the SoC are big-endian. I hope we
never plop this device down with a CPU that's litle-endian.
The CPU is big endian and the peripheral and bus to access the
peripheral are native endian, so also big endian in that case.
The newer SoCs are ARM-based and are little endian, but we already have
a clock driver for those.
--
Florian
