On Fri, Mar 10, 2023 at 09:35:01PM +0900, Yoshihiro Shimoda wrote: > Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) > PCIe endpoint module. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> Looking good now. Thanks. Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx> -Serge(y) > --- > .../bindings/pci/rcar-gen4-pci-ep.yaml | 97 +++++++++++++++++++ > 1 file changed, 97 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > new file mode 100644 > index 000000000000..12d779a4ce8d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml > @@ -0,0 +1,97 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas R-Car Gen4 PCIe Endpoint > + > +maintainers: > + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > + > +allOf: > + - $ref: snps,dw-pcie-ep.yaml# > + > +properties: > + compatible: > + items: > + - const: renesas,r8a779f0-pcie-ep # R-Car S4-8 > + - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 > + > + reg: > + maxItems: 5 > + > + reg-names: > + items: > + - const: dbi > + - const: atu > + - const: dma > + - const: app > + - const: addr_space > + > + interrupts: > + maxItems: 3 > + > + interrupt-names: > + items: > + - const: dma > + - const: sft_ce > + - const: app > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + max-functions: > + maximum: 2 > + > + max-link-speed: > + maximum: 4 > + > + num-lanes: > + maximum: 4 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - resets > + - power-domains > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/r8a779f0-sysc.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie0_ep: pcie-ep@e65d0000 { > + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep"; > + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, > + <0 0xe65d5000 0 0x1200>, <0 0xe65d6200 0 0x0e00>, > + <0 0xfe000000 0 0x400000>; > + reg-names = "dbi", "atu", "dma", "app", "addr_space"; > + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dma", "sft_ce", "app"; > + clocks = <&cpg CPG_MOD 624>; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 624>; > + num-lanes = <2>; > + max-link-speed = <2>; > + }; > + }; > -- > 2.25.1 > >
