On Tue, 14 Feb 2023 12:40:35 PST (-0800), Conor Dooley wrote:
Hey all,
On Sat, Feb 11, 2023 at 05:18:10AM +0200, Cristian Ciocaltea wrote:
Document the compatible for the SiFive Composable Cache Controller found
on the StarFive JH7100 SoC.
This also requires extending the 'reg' property to handle distinct
ranges, as specified via 'reg-names'.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
---
.../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index 31d20efaa6d3..2b864b2f12c9 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -25,6 +25,7 @@ select:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
required:
- compatible
@@ -37,6 +38,7 @@ properties:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- const: cache
- items:
- const: starfive,jh7110-ccache
@@ -70,7 +72,13 @@ properties:
- description: DirFail interrupt
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: control
+ - const: sideband
So why is this called "sideband"?
In the docs for the JH7100 it is called LIM & it's called LIM in our
docs for the PolarFire SoC (at the same address btw) and we run the HSS
IIRC it's both: "LIM" is the memory, "sideband" is the port. I can't
find any proper documentation of "sideband" outside of DT and errata,
but there's a hanful of references to it in the bootloader for the
fu540:
<https://github.com/sifive/freedom-u540-c000-bootloader/search?q=sideband>.
It's not really clear which is more correct here: sideband accesses are
only useful when the cache is configured as an LIM, at least for general
software. IIRC the accesses to the LIM only go through the sideband
port for the E core, but I might be wrong about that.
out of it! LIM being "loosely integrated memory", which by the limit
hits on Google may be a SiFive-ism?
Yep: TIM is the SiFive version of Arm's TCM (tightly coupled memory),
and LIM is the flavor that's farther away (L2 instead of L1).
I'm not really sure if adding it as a "reg" section is the right thing
to do as it's not "just" a register bank.
Perhaps Rob/Krzysztof have a take on that one?
next-level-cache: true
@@ -89,6 +97,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@@ -106,12 +115,29 @@ allOf:
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7100-ccache
+
+ then:
+ properties:
+ reg:
+ maxItems: 2
+
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
- if:
properties:
compatible:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
--
2.39.1
