Re: [PATCH v1 2/2] DT: eFuse: Add binding document for IMG Pistachio eFuse Controller

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Hi Arul,

On 11/18/14 12:37, Arul Ramasamy wrote:

Hi James Hartley and Ezequiel,

> On Mon, Nov 17, 2014 at 3:34 PM, Naidu Tellapati <Naidu.Tellapati@xxxxxxxxxx <mailto:Naidu.Tellapati@xxxxxxxxxx>> wrote:

>> Hi Andrew,

>>

>> Many thanks for the review.

>>

>>> +++ b/Documentation/devicetree/bindings/soc/pistachio/img-efuse.txt

>>> @@ -0,0 +1,18 @@

>>> +* IMG Pistachio eFuse controller

>>> +

>>> +Required properties:

>>> +- compatible: Must be "img,pistachio-efuse".

>>> +- reg: Must contain the base address and length of the eFuse registers.

>>> +- clocks: Must contain an entry for each entry in clock-names.

>>> + See ../clock/clock-bindings.txt for details.

>>> +- clock-names: Must include the following entries:

>>> + - efuse: External oscillator clock

>>

>> How is the external oscillator related to efuse? Also, perhaps it

>> should be called "osc" since it's not an efuse-specific clock.

>>

> This is what I read from the eFuse Controller TRM (Generic eFuse

> Controller.Technical Reference Manual.pdf) with respect to this clock.

>>

> > "Free-running oscillator clock – used to clock the fuse-unload state machine. < 50Mhz"

>>

>> Please comment.

> Hmm.. is this the 52Mhz external oscillator on Pistachio? Or something else?

Could you please help us might be with a help of our Hardware team.

The state machine is clocked at XTAL freq (which is 52MHz normally). The register interface is driven by the sys_clk (typically 400MHz)

>>> + - sys: eFuse system interface clock

>>

>> I don't see a system interface gate clock for efuse in the TRM ...

>

>> This is what I read from the above document about the sys_clk.

>

>> "System bus clock, synchronous to the IMGBus1 input. < 400 MHz."

>>

>> I think this clock enables access to shadow RAM where the eFuses status is stored.

> I don't see a bit in CR_PERIP_CLKEN that corresponds to this... Is this clock derived directly from SYSCLKOUT or PERIPHSYSCLKOUT (i.e. no gate specifically for efuse)?

Could you please help us might be with a help of our Hardware team.

It is not clock gated, it's fed directly from the PERIPH_SYS_CLK_OUT.

Thanks and Regards,

R.Arul Raj

Thanks,
James
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