On 14/03/2023 13:43, Xingyu Wu wrote: > Add bindings for the System-Top-Group clock and reset generator (STGCRG) > on the JH7110 RISC-V SoC by StarFive Ltd. > > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > --- > .../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++ > .../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++ > .../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++ > 3 files changed, 144 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
