Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index a9700654b421..27c35a657b15 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -564,9 +564,11 @@ dmac: dma-controller@11820000 {
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
+ clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_DMAC_ARESETN>,
<&cpg R9A07G043_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 79cffbf20c55..7b68bbebb5bd 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -740,9 +740,11 @@ dmac: dma-controller@11820000 {
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+ clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_DMAC_ARESETN>,
<&cpg R9A07G044_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index c0ae9c7c10fc..cc11e5855d62 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -746,9 +746,11 @@ dmac: dma-controller@11820000 {
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
+ clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_DMAC_ARESETN>,
<&cpg R9A07G054_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
--
2.25.1
