The property is utilized to set the CSR-MDC clock selector in the STMMAC
driver. The specified value is used instead of auto-detecting the
CSR/application clocks divider based on the reference clock rate. Let's
add a more detailed description to clarify the property purpose and
permitted values. In the later case the constraints are specified based on
the DW *MAC CR registers permitted values.
Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/net/snps,dwmac.yaml | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 224f8f70db85..edef405766e4 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -427,7 +427,15 @@ properties:
snps,clk-csr:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- Frequency division factor for MDC clock.
+ CSR-MDC clock selector. It sets up a divider of the CSR/application
+ clock to create an MDC signal with desired frequency. Note the
+ property value doesn't specify the divider itself by encodes the
+ corresponding divider value specific to the IP-core.
+ DW GMAC 0 - 42, 1 - 62, 2 - 16, 3 - 26, 4 - 102, 5 - 124, 8 - 4,
+ 9 - 6, 10 - 8, 11 - 10, 12 - 12, 13 - 14, 14 - 16, 15 - 18.
+ DW xGMAC 0 - 62, 1 - 102, 2 - 122, 3 - 142, 4 - 162, 5 - 202.
+ minimum: 0
+ maximum: 15
mdio:
$ref: mdio.yaml#
--
2.39.2
