Add description for additional nodes needed to support
mulitple channel DDR configurations in LLCC.
Signed-off-by: Komal Bajaj <quic_kbajaj@xxxxxxxxxxx>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index 38efcad56dbd..9a4a76caf490 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -37,15 +37,24 @@ properties:
items:
- description: LLCC base register region
- description: LLCC broadcast base register region
+ - description: Feature register to decide which LLCC configuration
+ to use, this is optional
reg-names:
items:
- const: llcc_base
- const: llcc_broadcast_base
+ - const: multi_channel_register
interrupts:
maxItems: 1
+ multi-ch-bit-off:
+ items:
+ - description: Specifies the offset in bits into the multi_channel_register
+ and the number of bits used to decide which LLCC configuration
+ to use
+
required:
- compatible
- reg
--
2.39.1
