> +static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
> +{
> + u32 val_lower, val_upper;
> + u64 val;
> +
> + if (counter == CYCLES_COUNTER) {
> + val_upper = readl_relaxed(pmu->base + PMC(counter) +
> 0x4);
> + val_lower = readl_relaxed(pmu->base + PMC(counter));
> + val = val_upper;
> + val = (val << 32);
> + val |= val_lower;
Read 64bit counter value need use below logic
do{
val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4);
val_lower = readl_relaxed(pmu->base + PMC(counter));
while( val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4));
assume upper is 0, when cpu read lower register, upper may change to 1,
so you will get wrong 64bit value.
Frank
> + } else {
> + val = readl_relaxed(pmu->base + PMC(counter));
> + }
> +
> + return val;
> +}
> +
> +static void ddr_perf_counter_global_config(struct ddr_pmu *pmu, bool
> enable)
> +{
> + u32 ctrl;
> +
> + ctrl = readl_relaxed(pmu->base + PMGC0);
> +
> + if (enable) {
> + /*
> + * The performance monitor must be reset before event
> counting
> + * sequences. The performance monitor can be reset by first
> freezing
> + * one or more counters and then clearing the freeze
> condition to
> + * allow the counters to count according to the settings in the
> + * performance monitor registers. Counters can be frozen
> individually
> + * by setting PMLCAn[FC] bits, or simultaneously by setting
> PMGC0[FAC].
> + * Simply clearing these freeze bits will then allow the
> performance
> + * monitor to begin counting based on the register settings.
> + */
> + ctrl |= PMGC0_FAC;
> + writel(ctrl, pmu->base + PMGC0);
> +
> + /*
> + * Freeze all counters disabled, interrupt enabled, and freeze
> + * counters on condition enabled.
> + */
> + ctrl &= ~PMGC0_FAC;
> + ctrl |= PMGC0_PMIE | PMGC0_FCECE;
> + writel(ctrl, pmu->base + PMGC0);
> + } else {
> + ctrl |= PMGC0_FAC;
> + ctrl &= ~(PMGC0_PMIE | PMGC0_FCECE);
> + writel(ctrl, pmu->base + PMGC0);
> + }
> +}
> +
> +static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
> + int counter, bool enable)
> +{
> + u32 ctrl_a;
> +
> + ctrl_a = readl_relaxed(pmu->base + PMLCA(counter));
> +
> + if (enable) {
> + ctrl_a |= PMLCA_FC;
> + writel(ctrl_a, pmu->base + PMLCA(counter));
> +
> + ddr_perf_clear_counter(pmu, counter);
> +
> + /* Freeze counter disabled, condition enabled, and program
> event.*/
> + ctrl_a &= ~PMLCA_FC;
> + ctrl_a |= PMLCA_CE;
> + ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F);
> + ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF));
> + writel(ctrl_a, pmu->base + PMLCA(counter));
> + } else {
> + /* Freeze counter. */
> + ctrl_a |= PMLCA_FC;
> + writel(ctrl_a, pmu->base + PMLCA(counter));
> + }
> +}
> +
> +static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1,
> int cfg2)
> +{
> + u32 pmcfg1, pmcfg2;
> + int event, counter;
> +
> + event = cfg & 0x000000FF;
> + counter = (cfg & 0x0000FF00) >> 8;
> +
> + pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
> +
> + if (counter == 2 && event == 73)
> + pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN;
> + else if (counter == 2 && event != 73)
> + pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN;
> +
> + if (counter == 3 && event == 73)
> + pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN;
> + else if (counter == 3 && event != 73)
> + pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN;
> +
> + if (counter == 4 && event == 73)
> + pmcfg1 |= PMCFG1_RD_BT_FILT_EN;
> + else if (counter == 4 && event != 73)
> + pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
> +
> + pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
> + pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2);
> + writel(pmcfg1, pmu->base + PMCFG1);
> +
> + pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
> + pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
> + pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1);
> + writel(pmcfg2, pmu->base + PMCFG2);
> +}
> +
> +static void ddr_perf_event_update(struct perf_event *event)
> +{
> + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + int counter = hwc->idx;
> + u64 new_raw_count;
> +
> + new_raw_count = ddr_perf_read_counter(pmu, counter);
> + local64_add(new_raw_count, &event->count);
> +
> + /* clear counter's value every time */
> + ddr_perf_clear_counter(pmu, counter);
> +}
> +
> +static int ddr_perf_event_init(struct perf_event *event)
> +{
> + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + struct perf_event *sibling;
> +
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + if (is_sampling_event(event) || event->attach_state &
> PERF_ATTACH_TASK)
> + return -EOPNOTSUPP;
> +
> + if (event->cpu < 0) {
> + dev_warn(pmu->dev, "Can't provide per-task data!\n");
> + return -EOPNOTSUPP;
> + }
> +
> + /*
> + * We must NOT create groups containing mixed PMUs, although
> software
> + * events are acceptable (for example to create a CCN group
> + * periodically read when a hrtimer aka cpu-clock leader triggers).
> + */
> + if (event->group_leader->pmu != event->pmu &&
> + !is_software_event(event->group_leader))
> + return -EINVAL;
> +
> + for_each_sibling_event(sibling, event->group_leader) {
> + if (sibling->pmu != event->pmu &&
> + !is_software_event(sibling))
> + return -EINVAL;
> + }
> +
> + event->cpu = pmu->cpu;
> + hwc->idx = -1;
> +
> + return 0;
> +}
> +
> +static void ddr_perf_event_start(struct perf_event *event, int flags)
> +{
> + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + int counter = hwc->idx;
> +
> + local64_set(&hwc->prev_count, 0);
> +
> + ddr_perf_counter_local_config(pmu, event->attr.config, counter,
> true);
> + hwc->state = 0;
> +}
> +
> +static int ddr_perf_event_add(struct perf_event *event, int flags)
> +{
> + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + int cfg = event->attr.config;
> + int cfg1 = event->attr.config1;
> + int cfg2 = event->attr.config2;
> + int counter;
> +
> + counter = (cfg & 0x0000FF00) >> 8;
> +
> + pmu->events[counter] = event;
> + pmu->active_events++;
> + hwc->idx = counter;
> + hwc->state |= PERF_HES_STOPPED;
> +
> + if (flags & PERF_EF_START)
> + ddr_perf_event_start(event, flags);
> +
> + /* read trans, write trans, read beat */
> + ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
> +
> + return 0;
> +}
> +
> +static void ddr_perf_event_stop(struct perf_event *event, int flags)
> +{
> + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + int counter = hwc->idx;
> +
> + ddr_perf_counter_local_config(pmu, event->attr.config, counter,
> false);
> + ddr_perf_event_update(event);
> +
> + hwc->state |= PERF_HES_STOPPED;
> +}
> +
> +static void ddr_perf_event_del(struct perf_event *event, int flags)
> +{
> + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> +
> + ddr_perf_event_stop(event, PERF_EF_UPDATE);
> +
> + pmu->active_events--;
> + hwc->idx = -1;
> +}
> +
> +static void ddr_perf_pmu_enable(struct pmu *pmu)
> +{
> + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
> +
> + ddr_perf_counter_global_config(ddr_pmu, true);
> +}
> +
> +static void ddr_perf_pmu_disable(struct pmu *pmu)
> +{
> + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
> +
> + ddr_perf_counter_global_config(ddr_pmu, false);
> +}
> +
> +static void ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
> + struct device *dev)
> +{
> + *pmu = (struct ddr_pmu) {
> + .pmu = (struct pmu) {
> + .module = THIS_MODULE,
> + .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
> + .task_ctx_nr = perf_invalid_context,
> + .attr_groups = attr_groups,
> + .event_init = ddr_perf_event_init,
> + .add = ddr_perf_event_add,
> + .del = ddr_perf_event_del,
> + .start = ddr_perf_event_start,
> + .stop = ddr_perf_event_stop,
> + .read = ddr_perf_event_update,
> + .pmu_enable = ddr_perf_pmu_enable,
> + .pmu_disable = ddr_perf_pmu_disable,
> + },
> + .base = base,
> + .dev = dev,
> + };
> +}
> +
> +static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
> +{
> + struct ddr_pmu *pmu = (struct ddr_pmu *)p;
> + struct perf_event *event;
> + int i;
> +
> + /*
> + * Counters can generate an interrupt on an overflow when msb of a
> + * counter changes from 0 to 1. For the interrupt to be signalled,
> + * below condition mush be satisfied:
> + * PMGC0[PMIE] = 1, PMGC0[FCECE] = 1, PMLCAn[CE] = 1
> + * When an interrupt is signalled, PMGC0[FAC] is set by hardware and
> + * all of the registers are frozen.
> + * Software can clear the interrupt condition by resetting the
> performance
> + * monitor and clearing the most significant bit of the counter that
> + * generate the overflow.
> + */
> + for (i = 0; i < NUM_COUNTERS; i++) {
> + if (!pmu->events[i])
> + continue;
> +
> + event = pmu->events[i];
> +
> + ddr_perf_event_update(event);
> + }
> +
> + ddr_perf_counter_global_config(pmu, true);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu,
> node);
> + int target;
> +
> + if (cpu != pmu->cpu)
> + return 0;
> +
> + target = cpumask_any_but(cpu_online_mask, cpu);
> + if (target >= nr_cpu_ids)
> + return 0;
> +
> + perf_pmu_migrate_context(&pmu->pmu, cpu, target);
> + pmu->cpu = target;
> +
> + WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)));
> +
> + return 0;
> +}
> +
> +static int ddr_perf_probe(struct platform_device *pdev)
> +{
> + struct ddr_pmu *pmu;
> + void __iomem *base;
> + int ret, irq;
> + char *name;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
> + if (!pmu)
> + return -ENOMEM;
> +
> + ddr_perf_init(pmu, base, &pdev->dev);
> +
> + pmu->devtype_data = of_device_get_match_data(&pdev->dev);
> +
> + platform_set_drvdata(pdev, pmu);
> +
> + pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL);
> + name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> DDR_PERF_DEV_NAME "%d", pmu->id);
> + if (!name) {
> + ret = -ENOMEM;
> + goto format_string_err;
> + }
> +
> + pmu->cpu = raw_smp_processor_id();
> + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> DDR_CPUHP_CB_NAME,
> + NULL, ddr_perf_offline_cpu);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to add callbacks for multi
> state\n");
> + goto cpuhp_state_err;
> + }
> + pmu->cpuhp_state = ret;
> +
> + /* Register the pmu instance for cpu hotplug */
> + ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu-
> >node);
> + if (ret) {
> + dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
> + goto cpuhp_instance_err;
> + }
> +
> + /* Request irq */
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(&pdev->dev, "Failed to get irq: %d", irq);
> + ret = irq;
> + goto ddr_perf_err;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, irq, ddr_perf_irq_handler,
> + IRQF_NOBALANCING | IRQF_NO_THREAD,
> + DDR_CPUHP_CB_NAME, pmu);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Request irq failed: %d", ret);
> + goto ddr_perf_err;
> + }
> +
> + pmu->irq = irq;
> + ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu));
> + if (ret) {
> + dev_err(pmu->dev, "Failed to set interrupt affinity\n");
> + goto ddr_perf_err;
> + }
> +
> + ret = perf_pmu_register(&pmu->pmu, name, -1);
> + if (ret)
> + goto ddr_perf_err;
> +
> + return 0;
> +
> +ddr_perf_err:
> + cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu-
> >node);
> +cpuhp_instance_err:
> + cpuhp_remove_multi_state(pmu->cpuhp_state);
> +cpuhp_state_err:
> +format_string_err:
> + ida_simple_remove(&ddr_ida, pmu->id);
> + dev_warn(&pdev->dev, "i.MX9 DDR Perf PMU failed (%d),
> disabled\n", ret);
> + return ret;
> +}
> +
> +static int ddr_perf_remove(struct platform_device *pdev)
> +{
> + struct ddr_pmu *pmu = platform_get_drvdata(pdev);
> +
> + cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu-
> >node);
> + cpuhp_remove_multi_state(pmu->cpuhp_state);
> +
> + perf_pmu_unregister(&pmu->pmu);
> +
> + ida_simple_remove(&ddr_ida, pmu->id);
> +
> + return 0;
> +}
> +
> +static struct platform_driver imx_ddr_pmu_driver = {
> + .driver = {
> + .name = "imx9-ddr-pmu",
> + .of_match_table = imx_ddr_pmu_dt_ids,
> + .suppress_bind_attrs = true,
> + },
> + .probe = ddr_perf_probe,
> + .remove = ddr_perf_remove,
> +};
> +module_platform_driver(imx_ddr_pmu_driver);
> +
> +MODULE_AUTHOR("Xu Yang <xu.yang_2@xxxxxxx>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("DDRC PerfMon for i.MX9 SoCs");
> --
> 2.34.1
