Add the missing cache-controller node. This will allow migration to the
generic l2c OF initialization.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
---
Note: This depends on "[PATCH v5 7/8] ARM: shmobile: r8a7740 dtsi: Add
PM domain support" due to the pd_a3sm reference.
---
arch/arm/boot/dts/r8a7740.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index e2c9496c2c325a1f..a9c7a986c0e9eca6 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -37,6 +37,17 @@
<0xc2000000 0x1000>;
};
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xf0100000 0x1000>;
+ interrupts = <84>;
+ power-domains = <&pd_a3sm>;
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
