RE: [PATCH RFC 1/3] dt-bindings: clock: Add Renesas versa3 clock generator bindings

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Hi Krzysztof Kozlowski,

> Subject: Re: [PATCH RFC 1/3] dt-bindings: clock: Add Renesas versa3 clock
> generator bindings
> 
> On 09/03/2023 10:53, Biju Das wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> >> Sent: Thursday, March 9, 2023 9:44 AM
> >> To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>; Michael Turquette
> >> <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Rob
> >> Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> >> <krzysztof.kozlowski+dt@xxxxxxxxxx>
> >> Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; linux-renesas-
> >> soc@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx;
> >> devicetree@xxxxxxxxxxxxxxx; Fabrizio Castro
> >> <fabrizio.castro.jz@xxxxxxxxxxx>
> >> Subject: Re: [PATCH RFC 1/3] dt-bindings: clock: Add Renesas versa3
> >> clock generator bindings
> >>
> >> On 09/03/2023 10:18, Biju Das wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> >>>> Sent: Thursday, March 9, 2023 9:14 AM
> >>>> To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>; Michael Turquette
> >>>> <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Rob
> >>>> Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> >>>> <krzysztof.kozlowski+dt@xxxxxxxxxx>
> >>>> Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; linux-renesas-
> >>>> soc@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx;
> >>>> devicetree@xxxxxxxxxxxxxxx; Fabrizio Castro
> >>>> <fabrizio.castro.jz@xxxxxxxxxxx>
> >>>> Subject: Re: [PATCH RFC 1/3] dt-bindings: clock: Add Renesas versa3
> >>>> clock generator bindings
> >>>>
> >>>> On 09/03/2023 08:57, Biju Das wrote:
> >>>>>>> It is clk generator HW specific. Clk generator is vital
> >>>>>>> component which provides clocks to the system.
> >>>>>>
> >>>>>> Every clock controller is vital...
> >>>>>>
> >>>>>>> We are providing some hardware feature which is exposed as dt
> >>>>>>> properties.
> >>>>>>>
> >>>>>>> Like clock output is fixed rate clock or dynamic rate clock/
> >>>>>>
> >>>>>> OK, I wait then for proper description which will explain and
> >>>>>> justify
> >>>> this.
> >>>>>
> >>>>> Here it is, Please let me know is it ok?
> >>>>>
> >>>>> renesas,output-clock-fixed-rate-mode:
> >>>>>     type: boolean
> >>>>>     description:
> >>>>>       In output clock fixed rate mode, the output clock frequency
> >>>>> is
> >>>> always
> >>>>>       fixed and the hardware will use the values from the OTP or
> >>>>> full
> >>>> register
> >>>>> 	map initialized during boot.
> >>>>>       If not given, the output clock rate is not fixed.
> >>>>>     maxItems: 6
> >>>>
> >>>> boolean is scalar, not array, so no maxItems. If the frequency is
> >>>> taken from OTP or register map, why they cannot also provide
> >>>> information the clock is fixed?
> >>>
> >>> OK, I will make an array property instead. From HW perspective each
> >>> clock output from the Clock generator is controllable ie, fixed rate
> >>> or
> >> dynamic rate.
> >>>
> >>> If all the output clocks are fixed rate one, then frequency is taken
> >>> from OTP or register map. But if any one clock output generates
> >>> dynamic rate, then it uses dynamic settings.
> >>
> >> Second try, same question, let me know if it is not clear:
> >>
> >> "why they cannot also provide information the clock is fixed?"
> >
> > This information we are providing through dt.
> 
> No, you are not. We just discuss it. If we do not agree, you are not going
> to provide information through DT.
> 
> >
> > It is a complex clock generator which provides 6 HW clock outputs.
> > The 6 HW clock outputs can be individually controllable to generate
> > Either fixed frequency or dynamic frequency.
> 
> Ah, indeed. 6 clock outputs prohibits configuring this from OTP. If only
> there were 5 outputs then it would be possible...
> 
> >
> >  Output clk1 "diff2",
> >  Output clk2 "diff1",
> >  Output clk3 "se3",
> >  Output clk4 "se2",
> >  Output clk5 "se1",
> >  Output clk6 "ref"
> >
> > I want to make "Output clk4" from clock generator as dynamic frequency
> > one And make other clock frequency from clock generator as fixed one.
> >
> > How do you describe this in dt? Please share your thoughts.
> 
> Read from OTP or registers.

Looks no other option. So will drop this property and match the one from OTP with full regmap.

Cheers,
Biju





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