On 6.03.2023 18:08, Lux Aliaga wrote:
> Adds a UFS host controller node and its corresponding PHY to
> the sm6125 platform.
>
> Signed-off-by: Lux Aliaga <they@xxxxxxxxx>
> ---
[...]
> + ufs_mem_phy: phy@4807000 {
> + compatible = "qcom,sm6125-qmp-ufs-phy";
> + reg = <0x04807000 0xdb8>;
> +
> + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> + clock-names = "ref", "ref_aux";
Please wrap it into
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref",
"ref_aux";
and resolve the binding/offset situation. Otherwise, LGTM!
Konrad
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + power-domains = <&gcc UFS_PHY_GDSC>;
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> gpi_dma0: dma-controller@4a00000 {
> compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
> reg = <0x04a00000 0x60000>;
