To be reused with other Hi3798 series SoCs.
Signed-off-by: David Yang <mmyangfl@xxxxxxxxx>
---
drivers/clk/hisilicon/crg-hi3798.c | 238 ++++++++++++++++-------------
1 file changed, 136 insertions(+), 102 deletions(-)
diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c
index 7e9507de2..2477c1208 100644
--- a/drivers/clk/hisilicon/crg-hi3798.c
+++ b/drivers/clk/hisilicon/crg-hi3798.c
@@ -59,6 +59,124 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = {
{ HI3798_FIXED_250M, "250m", NULL, 0, 250000000, },
};
+struct hi3798_crg_clks {
+ const struct hisi_phase_clock *phase_clks;
+ int phase_clks_nums;
+ const struct hisi_mux_clock *mux_clks;
+ int mux_clks_nums;
+ const struct hisi_gate_clock *gate_clks;
+ int gate_clks_nums;
+};
+
+static struct hisi_clock_data *hi3798_clk_register(
+ struct platform_device *pdev, const struct hi3798_crg_clks *clks)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ /* hisi_phase_clock is resource managed */
+ ret = hisi_clk_register_phase(&pdev->dev, clks->phase_clks,
+ clks->phase_clks_nums, clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks,
+ ARRAY_SIZE(hi3798_fixed_rate_clks),
+ clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = hisi_clk_register_mux(clks->mux_clks, clks->mux_clks_nums, clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_gate:
+ hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
+ ARRAY_SIZE(hi3798_fixed_rate_clks),
+ clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3798_clk_unregister(
+ struct platform_device *pdev, const struct hi3798_crg_clks *clks)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data);
+ hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, crg->clk_data);
+ hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
+ ARRAY_SIZE(hi3798_fixed_rate_clks),
+ crg->clk_data);
+}
+
+/* hi3798 sysctrl CRG */
+
+#define HI3798_SYSCTRL_NR_CLKS 16
+
+struct hi3798_sysctrl_clks {
+ const struct hisi_gate_clock *gate_clks;
+ int gate_clks_nums;
+};
+
+static struct hisi_clock_data *hi3798_sysctrl_clk_register(
+ struct platform_device *pdev, const struct hi3798_sysctrl_clks *clks)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_gate:
+ hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3798_sysctrl_clk_unregister(
+ struct platform_device *pdev, const struct hi3798_sysctrl_clks *clks)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data);
+}
+
+/* hi3798CV200 */
+
static const char *const hi3798cv200_mmc_mux_p[] = {
"100m", "50m", "25m", "200m", "150m" };
static u32 hi3798cv200_mmc_mux_table[] = {0, 1, 2, 3, 6};
@@ -194,79 +312,24 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
};
+static const struct hi3798_crg_clks hi3798cv200_crg_clks_data = {
+ .phase_clks = hi3798cv200_phase_clks,
+ .phase_clks_nums = ARRAY_SIZE(hi3798cv200_phase_clks),
+ .mux_clks = hi3798cv200_mux_clks,
+ .mux_clks_nums = ARRAY_SIZE(hi3798cv200_mux_clks),
+ .gate_clks = hi3798cv200_gate_clks,
+ .gate_clks_nums = ARRAY_SIZE(hi3798cv200_gate_clks),
+};
+
static struct hisi_clock_data *hi3798cv200_clk_register(
struct platform_device *pdev)
{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- /* hisi_phase_clock is resource managed */
- ret = hisi_clk_register_phase(&pdev->dev,
- hi3798cv200_phase_clks,
- ARRAY_SIZE(hi3798cv200_phase_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks,
- ARRAY_SIZE(hi3798_fixed_rate_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
- ARRAY_SIZE(hi3798cv200_mux_clks),
- clk_data);
- if (ret)
- goto unregister_fixed_rate;
-
- ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
- ARRAY_SIZE(hi3798cv200_gate_clks),
- clk_data);
- if (ret)
- goto unregister_mux;
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_gate:
- hisi_clk_unregister_gate(hi3798cv200_gate_clks,
- ARRAY_SIZE(hi3798cv200_gate_clks),
- clk_data);
-unregister_mux:
- hisi_clk_unregister_mux(hi3798cv200_mux_clks,
- ARRAY_SIZE(hi3798cv200_mux_clks),
- clk_data);
-unregister_fixed_rate:
- hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
- ARRAY_SIZE(hi3798_fixed_rate_clks),
- clk_data);
- return ERR_PTR(ret);
+ return hi3798_clk_register(pdev, &hi3798cv200_crg_clks_data);
}
static void hi3798cv200_clk_unregister(struct platform_device *pdev)
{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3798cv200_gate_clks,
- ARRAY_SIZE(hi3798cv200_gate_clks),
- crg->clk_data);
- hisi_clk_unregister_mux(hi3798cv200_mux_clks,
- ARRAY_SIZE(hi3798cv200_mux_clks),
- crg->clk_data);
- hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks,
- ARRAY_SIZE(hi3798_fixed_rate_clks),
- crg->clk_data);
+ hi3798_clk_unregister(pdev, &hi3798cv200_crg_clks_data);
}
static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
@@ -274,10 +337,6 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
.unregister_clks = hi3798cv200_clk_unregister,
};
-/* hi3798 sysctrl CRG */
-
-#define HI3798_SYSCTRL_NR_CLKS 16
-
static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
{ HISTB_IR_CLK, "clk_ir", "24m",
CLK_SET_RATE_PARENT, 0x48, 4, 0, },
@@ -287,45 +346,20 @@ static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
CLK_SET_RATE_PARENT, 0x48, 10, 0, },
};
+static const struct hi3798_sysctrl_clks hi3798cv200_sysctrl_clks_data = {
+ .gate_clks = hi3798cv200_sysctrl_gate_clks,
+ .gate_clks_nums = ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+};
+
static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
struct platform_device *pdev)
{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
- ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_gate:
- hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
- ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
- clk_data);
- return ERR_PTR(ret);
+ return hi3798_sysctrl_clk_register(pdev, &hi3798cv200_sysctrl_clks_data);
}
static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
{
- struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
- ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
- crg->clk_data);
+ hi3798_sysctrl_clk_unregister(pdev, &hi3798cv200_sysctrl_clks_data);
}
static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
--
2.39.2
