On Sat, Feb 11, 2023 at 05:18:12AM +0200, Cristian Ciocaltea wrote: > From: Emil Renner Berthing <kernel@xxxxxxxx> > > This adds support for the StarFive JH7100 SoC which also feature this > SiFive cache controller. > > Unfortunately the interrupt for uncorrected data is broken on the JH7100 > and fires continuously, so add a quirk to not register a handler for it. > > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> > [drop JH7110, rework Kconfig] > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx> This driver doesn't really do very much of anything as things stand, so I don't see really see all that much value in picking it up right now, since the non-coherent bits aren't usable yet. > --- > drivers/soc/sifive/Kconfig | 1 + > drivers/soc/sifive/sifive_ccache.c | 11 ++++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig > index e86870be34c9..867cf16273a4 100644 > --- a/drivers/soc/sifive/Kconfig > +++ b/drivers/soc/sifive/Kconfig > @@ -4,6 +4,7 @@ if SOC_SIFIVE || SOC_STARFIVE > > config SIFIVE_CCACHE > bool "Sifive Composable Cache controller" > + default SOC_STARFIVE I don't think this should have a default set w/ the support that this patch brings in. Perhaps later we should be doing defaulting, but not at this point in the series. Other than that, this is fine by me: Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Thanks, Conor.
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