On Mon, Mar 06, 2023 at 12:09:35PM +0100, Jerome Brunet wrote: > > On Wed 01 Mar 2023 at 21:37, Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> wrote: > > > From: Jian Hu <jian.hu@xxxxxxxxxxx> > > > > Modern meson PLL IPs are a little bit different from early known PLLs. > > The main difference is located in the init/enable/disable sequences; the > > rate logic is the same. > > For the record, I find very odd that PLLs used to have an 'rst' bit in > CTRL0:29 (see g12 for example), this bit goes un-documented in the a1 > datasheet, and following SoCs like s4 still have a rst bit, still in > CTRL0:29 > > I would not be surpized if the rst is actually still there in the a1. > It is just my guess ... > We don't know it for sure. Datasheet doesn't have any information about CTRL0:29 bit, CTRL0:28 (enable) bit is last one I see. Vendor Amlogic driver doesn't have it in the init sequence as well. BTW, vendor driver doesn't use clk_pll common logic, it achieves PLL power-on goals using init_regs sequence. > > Compared with the previous SoCs, self-adaption current module > > is newly added for A1, and there is no reset parameter except the > > fixed pll. In A1 PLL, the PLL enable sequence is different, using > > the new power-on sequence to enable the PLL. > > Please split this patch: > #1 make the rst optional (if you must) > #2 add the self current adapt param. > > Apart from this, it looks good > Thank you, I'll split it in the next version! [...] -- Thank you, Dmitry
