On 06/03/2023 16:05, Krzysztof Kozlowski wrote: > On 20/02/2023 15:05, Sumit Gupta wrote: >> This patch series adds memory interconnect support for Tegra234 SoC. >> It is used to dynamically scale DRAM Frequency as per the bandwidth >> requests from different Memory Controller (MC) clients. >> MC Clients use ICC Framework's icc_set_bw() api to dynamically request >> for the DRAM bandwidth (BW). As per path, the request will be routed >> from MC to the EMC driver. MC driver passes the request info like the >> Client ID, type, and frequency request info to the BPMP-FW which will >> set the final DRAM freq considering all exisiting requests. >> >> MC and EMC are the ICC providers. Nodes in path for a request will be: >> Client[1-n] -> MC -> EMC -> EMEM/DRAM >> >> The patch series also adds interconnect support in below client drivers: >> 1) CPUFREQ driver for scaling bandwidth with CPU frequency. For that, >> added per cluster OPP table which will be used in the CPUFREQ driver >> by requesting the minimum BW respective to the given CPU frequency in >> the OPP table of given cluster. >> 2) PCIE driver to request BW required for different modes. > > No dependencies or ordering written, so I am free to take memory > controller bits, I assume. And not.. NAK, since you decided to ignore my comments. Really, we do not have time for such useless ping pong. Best regards, Krzysztof
