These symbols might cause confusion when adding support for other Hi3798
series SoCs.
Signed-off-by: David Yang <mmyangfl@xxxxxxxxx>
---
drivers/clk/hisilicon/crg-hi3798.c | 41 ++++++++++++-------------
include/dt-bindings/clock/histb-clock.h | 2 ++
2 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c
index 9c933172b..f834805d7 100644
--- a/drivers/clk/hisilicon/crg-hi3798.c
+++ b/drivers/clk/hisilicon/crg-hi3798.c
@@ -27,8 +27,6 @@
#define HI3798_FIXED_300M 73
#define HI3798_FIXED_400M 74
#define HI3798_MMC_MUX 75
-#define HI3798_ETH_PUB_CLK 76
-#define HI3798_ETH_BUS_CLK 77
#define HI3798_ETH_BUS0_CLK 78
#define HI3798_ETH_BUS1_CLK 79
#define HI3798_COMBPHY1_MUX 80
@@ -177,30 +175,31 @@ static void hi3798_sysctrl_clk_unregister(
/* hi3798CV200 */
-static const char *const mmc_mux_p[] = {
+static const char *const hi3798cv200_mmc_mux_p[] = {
"100m", "50m", "25m", "200m", "150m" };
-static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
+static u32 hi3798cv200_mmc_mux_table[] = {0, 1, 2, 3, 6};
-static const char *const comphy_mux_p[] = {
+static const char *const hi3798cv200_comphy_mux_p[] = {
"100m", "25m"};
-static u32 comphy_mux_table[] = {2, 3};
+static u32 hi3798cv200_comphy_mux_table[] = {2, 3};
-static const char *const sdio_mux_p[] = {
+static const char *const hi3798cv200_sdio_mux_p[] = {
"100m", "50m", "150m", "166p5m" };
-static u32 sdio_mux_table[] = {0, 1, 2, 3};
+static u32 hi3798cv200_sdio_mux_table[] = {0, 1, 2, 3};
static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
- { HI3798_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
- CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
- { HI3798_COMBPHY0_MUX, "combphy0_mux",
- comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
- CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
- { HI3798_COMBPHY1_MUX, "combphy1_mux",
- comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
- CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
- { HI3798_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
- ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
- 0x9c, 8, 2, 0, sdio_mux_table, },
+ { HI3798_MMC_MUX, "mmc_mux", hi3798cv200_mmc_mux_p,
+ ARRAY_SIZE(hi3798cv200_mmc_mux_p), CLK_SET_RATE_PARENT,
+ 0xa0, 8, 3, 0, hi3798cv200_mmc_mux_table, },
+ { HI3798_COMBPHY0_MUX, "combphy0_mux", hi3798cv200_comphy_mux_p,
+ ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT,
+ 0x188, 2, 2, 0, hi3798cv200_comphy_mux_table, },
+ { HI3798_COMBPHY1_MUX, "combphy1_mux", hi3798cv200_comphy_mux_p,
+ ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT,
+ 0x188, 10, 2, 0, hi3798cv200_comphy_mux_table, },
+ { HI3798_SDIO0_MUX, "sdio0_mux", hi3798cv200_sdio_mux_p,
+ ARRAY_SIZE(hi3798cv200_sdio_mux_p), CLK_SET_RATE_PARENT,
+ 0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, },
};
static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
@@ -253,9 +252,9 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
{ HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
/* Ethernet */
- { HI3798_ETH_PUB_CLK, "clk_pub", NULL,
+ { HISTB_ETH_PUB_CLK, "clk_pub", NULL,
CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
- { HI3798_ETH_BUS_CLK, "clk_bus", "clk_pub",
+ { HISTB_ETH_BUS_CLK, "clk_bus", "clk_pub",
CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
{ HI3798_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index e64e5770a..ed47c43c3 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -58,6 +58,8 @@
#define HISTB_USB3_UTMI_CLK1 48
#define HISTB_USB3_PIPE_CLK1 49
#define HISTB_USB3_SUSPEND_CLK1 50
+#define HISTB_ETH_PUB_CLK 51
+#define HISTB_ETH_BUS_CLK 52
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
--
2.39.1
