Re: [PATCH 7/7] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes

Devi Priya <quic_devipriy@xxxxxxxxxxx> · Fri, 3 Mar 2023 17:39:58 +0530

On 2/24/2023 12:27 PM, Kathiravan T wrote:

On 2/14/2023 10:11 PM, Devi Priya wrote:
Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.

Co-developed-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
Signed-off-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx>
---
  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  28 ++
  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 477 ++++++++++++++++++-
  2 files changed, 499 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts 
b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
index 2c8430197ec0..21b53f34ce84 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -8,6 +8,7 @@
  /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
  #include "ipq9574.dtsi"
  / {
@@ -29,6 +30,33 @@
      status = "okay";
  };
+&pcie1_phy {
+    status = "okay";
+};
+
+&pcie1_x1 {
+    perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+    status = "okay";
+};
+
+&pcie2_phy {
+    status = "okay";
+};
+
+&pcie2_x2 {
+    perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+    status = "okay";
+};
+
+&pcie3_phy {
+    status = "okay";
+};
+
+&pcie3_x2 {
+    perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+    status = "okay";
+};
+
  &sdhc_1 {
      pinctrl-0 = <&sdc_default_state>;
      pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi 
b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 062f80798ebb..a32dbdeb5bed 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -6,8 +6,8 @@
   * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights 
reserved.
   */
-#include <dt-bindings/interrupt-controller/arm-gic.h>
  #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
  #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
  / {
@@ -22,11 +22,41 @@
              #clock-cells = <0>;
          };
+        pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
+            compatible = "fixed-clock";
+            clock-frequency = <250000000>;
+            #clock-cells = <0>;
+        };
+
+        pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
+            compatible = "fixed-clock";
+            clock-frequency = <250000000>;
+            #clock-cells = <0>;
+        };
+
+        pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
+            compatible = "fixed-clock";
+            clock-frequency = <250000000>;
+            #clock-cells = <0>;
+        };
+
+        pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
+            compatible = "fixed-clock";
+            clock-frequency = <250000000>;
+            #clock-cells = <0>;
+        };
+
          sleep_clk: sleep-clk {
              compatible = "fixed-clock";
              #clock-cells = <0>;
          };
+        usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
+            compatible = "fixed-clock";
+            clock-frequency = <125000000>;
+            #clock-cells = <0>;
+        };
+
          xo_board_clk: xo-board-clk {
              compatible = "fixed-clock";
              #clock-cells = <0>;
@@ -121,6 +151,155 @@
          #size-cells = <1>;
          ranges = <0 0 0 0xffffffff>;
+        pcie0_phy: phy@84000 {
+            compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+            reg = <0x00084000 0x1bc>; /* Serdes PLL */
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;
+            clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+                 <&gcc GCC_PCIE0_AHB_CLK>,
+                 <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>,
+                 <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>;
+            clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+            assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
+            assigned-clock-rates = <20000000>;
+
+            resets = <&gcc GCC_PCIE0_PHY_BCR>,
+                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
+            reset-names = "phy", "common";
+
+            status = "disabled";
+
+            pcie0_lane: phy@84200 {
+                reg = <0x00084200 0x16c>, /* Serdes Tx */
+                      <0x00084400 0x200>, /* Serdes Rx */
+                      <0x00084800 0x1f0>, /* PCS: Lane0, COM, PCIE */
+                      <0x00084c00 0xf4>;  /* pcs_misc */
+                #phy-cells = <0>;
+
+                clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+                clock-names = "pipe0";
+                clock-output-names = "gcc_pcie0_pipe_clk_src";
+                #clock-cells = <0>;
+            };
+        };
+
+        pcie2_phy: phy@8c000 {
+            compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+            reg = <0x0008c000 0x1bc>; /* Serdes PLL */
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;
+
+            clocks = <&gcc GCC_PCIE2_AUX_CLK>,
+                 <&gcc GCC_PCIE2_AHB_CLK>,
+                 <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
+                 <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
+            clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+            assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
+            assigned-clock-rates = <20000000>;
+
+            resets = <&gcc GCC_PCIE2_PHY_BCR>,
+                 <&gcc GCC_PCIE2PHY_PHY_BCR>;
+            reset-names = "phy", "common";
+
+            status = "disabled";
+
+            pcie2_lanes: phy@8c200 {
+                reg = <0x0008c200 0x16c>, /* Serdes Tx0 */
+                      <0x0008c400 0x200>, /* Serdes Rx0 */
+                      <0x0008d000 0x1f0>, /* PCS: Lane0, COM, PCIE */
+                      <0x0008c600 0x16c>, /* Serdes Tx1 */
+                      <0x0008c800 0x200>, /* Serdes Rx1 */
+                      <0x0008d400 0x0f8>; /* pcs_misc */
+
+                #phy-cells = <0>;
+
+                clocks = <&gcc GCC_PCIE2_PIPE_CLK>;
+                clock-names = "pipe0";
+                clock-output-names = "gcc_pcie2_pipe_clk_src";
+                #clock-cells = <0>;
+            };
+        };
+
+        pcie3_phy: phy@f4000 {
+            compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+            reg = <0x000f4000 0x1bc>; /* Serdes PLL */
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;
+
+            clocks = <&gcc GCC_PCIE3_AUX_CLK>,
+                 <&gcc GCC_PCIE3_AHB_CLK>,
+                 <&gcc GCC_ANOC_PCIE3_2LANE_M_CLK>,
+                 <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
+            clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+            assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
+            assigned-clock-rates = <20000000>;
+
+            resets = <&gcc GCC_PCIE3_PHY_BCR>,
+                 <&gcc GCC_PCIE3PHY_PHY_BCR>;
+            reset-names = "phy", "common";
+
+            status = "disabled";
+
+            pcie3_lanes: phy@f4200 {
+                reg = <0x000f4200 0x16c>, /* Serdes Tx0 */
+                      <0x000f4400 0x200>, /* Serdes Rx0 */
+                      <0x000f5000 0x1f0>, /* PCS: Lane0, COM, PCIE */
+                      <0x000f4600 0x16c>, /* Serdes Tx1 */
+                      <0x000f4800 0x200>, /* Serdes Rx1 */
+                      <0x000f5400 0x0f8>; /* pcs_misc */
+
+                #phy-cells = <0>;
+
+                clocks = <&gcc GCC_PCIE3_PIPE_CLK>;
+                clock-names = "pipe0";
+                clock-output-names = "gcc_pcie3_pipe_clk_src";
+                #clock-cells = <0>;
+            };
+        };
+
+        pcie1_phy: phy@fc000 {
+            compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+            reg = <0x000fc000 0x1bc>; /* Serdes PLL */
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges;
+
+            clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+                 <&gcc GCC_PCIE1_AHB_CLK>,
+                 <&gcc GCC_ANOC_PCIE1_1LANE_M_CLK>,
+                 <&gcc GCC_SNOC_PCIE1_1LANE_S_CLK>;
+            clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane";
+
+            assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
+            assigned-clock-rates = <20000000>;
+
+            resets = <&gcc GCC_PCIE1_PHY_BCR>,
+                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
+            reset-names = "phy", "common";
+
+            status = "disabled";
+
+            pcie1_lane: phy@fc200 {
+                reg = <0x000fc200 0x16c>, /* Serdes Tx */
+                      <0x000fc400 0x200>, /* Serdes Rx */
+                      <0x000fc800 0x1f0>, /* PCS: Lane0, COM, PCIE */
+                      <0x000fcc00 0xf4>;  /* pcs_misc */
+                #phy-cells = <0>;
+
+                clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+                clock-names = "pipe0";
+                clock-output-names = "gcc_pcie1_pipe_clk_src";
+                #clock-cells = <0>;
+            };
+        };
+
          tlmm: pinctrl@1000000 {
              compatible = "qcom,ipq9574-tlmm";
              reg = <0x01000000 0x300000>;
@@ -145,11 +324,11 @@
              clocks = <&xo_board_clk>,
                   <&sleep_clk>,
                   <&bias_pll_ubi_nc_clk>,
-                 <0>,
-                 <0>,
-                 <0>,
-                 <0>,
-                 <0>;
+                 <&pcie30_phy0_pipe_clk>,
+                 <&pcie30_phy1_pipe_clk>,
+                 <&pcie30_phy2_pipe_clk>,
+                 <&pcie30_phy3_pipe_clk>,
+                 <&usb3phy_0_cc_pipe_clk>;


pipe clock source is PHY. So should we add the pcie_phy phandle here and 
use it like how it is done in other targets, ex: sm8550.dtsi?
Yes sure kathir. Will update this in the next series


              #clock-cells = <1>;
              #reset-cells = <1>;
              #power-domain-cells = <1>;
@@ -282,6 +461,292 @@
                  status = "disabled";
              };
          };
+
+        pcie1_x1: pci@10000000 {
+            compatible = "qcom,pcie-ipq9574";
+            reg =  <0x10000000 0xf1d>,
+                   <0x10000F20 0xa8>,
+                   <0x10001000 0x1000>,
+                   <0x000F8000 0x4000>,
+                   <0x10100000 0x1000>,
+                   <0x00618108 0x4>;
+            reg-names = "dbi", "elbi", "atu", "parf", "config", 
"aggr_noc";
+            device_type = "pci";
+            linux,pci-domain = <2>;
+            bus-range = <0x00 0xff>;
+            num-lanes = <1>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            ranges = <0x81000000 0 0x10200000 0x10200000
+                  0 0x00100000   /* downstream I/O */
+                  0x82000000 0 0x10300000 0x10300000
+                  0 0x07d00000>; /* non-prefetchable memory */
+
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0x7>;
+            interrupt-map = <0 0 0 1 &intc 0 35
+                    IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                    <0 0 0 2 &intc 0 49
+                    IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                    <0 0 0 3 &intc 0 84
+                    IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                    <0 0 0 4 &intc 0 85
+                    IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+            interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "global_irq";


Controller driver doesn't support the "global_irq" yet. Please correct 
me If I am wrong.


Thanks, Kathiravan T.

Regards,
Devi Priya






