Add documentation to describe StarFive Pulse Width Modulation controller driver. Signed-off-by: William Qiu <william.qiu@xxxxxxxxxxxxxxxx> --- .../devicetree/bindings/pwm/pwm-starfive.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-starfive.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-starfive.yaml b/Documentation/devicetree/bindings/pwm/pwm-starfive.yaml new file mode 100644 index 000000000000..4ba2a8cc5344 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-starfive.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-starfive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive PWM controller + +maintainers: + - William Qiu <william.qiu@xxxxxxxxxxxxxxxx> + +description: + StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates + binary signal with user-programmable low and high periods. Clock source for the + PWM can be either system clockor external clock. Each PWM timer block provides 8 + PWM channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - const: starfive,jh7110-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm@120d0000 { + compatible = "starfive,jh7110-pwm"; + reg = <0x120d0000 0x10000>; + clocks = <&syscrg 121>; + resets = <&syscrg 108>; + #pwm-cells=<3>; + }; -- 2.34.1
