On Tue, Feb 21, 2023 at 04:33:23PM +0800, Xingyu Wu wrote: > Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110 > System-Top-Group, Image-Signal-Process and Video-Output > clock and reset drivers for the JH7110 RISC-V SoC. > > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 59 ++++++++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index a5e6fb3ad188..697ab59191a1 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -6,6 +6,7 @@ > > /dts-v1/; > #include <dt-bindings/clock/starfive,jh7110-crg.h> > +#include <dt-bindings/power/starfive,jh7110-pmu.h> > #include <dt-bindings/reset/starfive,jh7110-crg.h> Please keep these sorted alphabetically, otherwise this *looks* fine to me. Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Thanks, Conor.
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