On Mon, Feb 20, 2023 at 05:52:52PM +0530, Sarath Babu Naidu Gaddam wrote:
> From: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx>
>
> Convert the bindings document for Xilinx AXI Ethernet Subsystem
> from txt to yaml. No changes to existing binding description.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx>
> Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@xxxxxxx>
> ---
> Changes in V6:
> 1) Addressed below review comments.
> a)add a $ref to ethernet-controller.yaml for pcs-handle.
> b)Drop unused labels(axi_ethernetlite_0_mdio).
> c)Not relevant to the binding(interrupt-parent).
>
> Changes in V5:
> 1) Removed .txt file which was missed in V4
>
> Changes in V4:
> 1)Changed the interrupts property and add allOf:if:then for it.
>
> Changes in V3:
> 1) Moved RFC to PATCH.
> 2) Addressed below review comments
> a) Indentation.
> b) maxItems:3 does not match your description.
> c) Filename matching compatibles.
>
> Changes in V2:
> 1) remove .txt and change the name of file to xlnx,axiethernet.yaml.
> 2) Fix DT check warning('device_type' does not match any of the regexes:
> 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/net
> /xilinx_axienet.yaml).
> ---
> .../bindings/net/xilinx_axienet.txt | 101 -----------
> .../bindings/net/xlnx,axi-ethernet.yaml | 165 ++++++++++++++++++
> MAINTAINERS | 1 +
> 3 files changed, 166 insertions(+), 101 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/net/xilinx_axienet.txt
> create mode 100644 Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
[...]
> +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> @@ -0,0 +1,165 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: AXI 1G/2.5G Ethernet Subsystem
> +
> +description: |
> + Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
> + provides connectivity to an external ethernet PHY supporting different
> + interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
> + segments of memory for buffering TX and RX, as well as the capability of
> + offloading TX/RX checksum calculation off the processor.
> +
> + Management configuration is done through the AXI interface, while payload is
> + sent and received through means of an AXI DMA controller. This driver
> + includes the DMA driver code, so this driver is incompatible with AXI DMA
> + driver.
> +
> +maintainers:
> + - Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx>
> +
> +properties:
> + compatible:
> + enum:
> + - xlnx,axi-ethernet-1.00.a
> + - xlnx,axi-ethernet-1.01.a
> + - xlnx,axi-ethernet-2.01.a
> +
> + reg:
> + description:
> + Address and length of the IO space, as well as the address
> + and length of the AXI DMA controller IO space, unless
> + axistream-connected is specified, in which case the reg
> + attribute of the node referenced by it is used.
> + maxItems: 2
> +
> + interrupts:
> + items:
> + - description: Ethernet core interrupt
> + - description: Tx DMA interrupt
> + - description: Rx DMA interrupt
> + description:
> + Ethernet core interrupt is optional. If axistream-connected property is
> + present DMA node should contains TX/RX DMA interrupts else DMA interrupt
> + resources are mentioned on ethernet node.
> + minItems: 1
> +
> + phy-handle: true
> +
> + xlnx,rxmem:
> + description:
> + Set to allocated memory buffer for Rx/Tx in the hardware.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + phy-mode: true
I'd assume only a subset of modes are supported by this h/w. If so, list
them.
> +
> + xlnx,phy-type:
> + description:
> + Do not use, but still accepted in preference to phy-mode.
> + deprecated: true
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + xlnx,txcsum:
> + description:
> + TX checksum offload. 0 or empty for disabling TX checksum offload,
> + 1 to enable partial TX checksum offload and 2 to enable full TX
> + checksum offload.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + xlnx,rxcsum:
> + description:
> + RX checksum offload. 0 or empty for disabling RX checksum offload,
> + 1 to enable partial RX checksum offload and 2 to enable full RX
> + checksum offload.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + xlnx,switch-x-sgmii:
> + type: boolean
> + description:
> + Indicate the Ethernet core is configured to support both 1000BaseX and
> + SGMII modes. If set, the phy-mode should be set to match the mode
> + selected on core reset (i.e. by the basex_or_sgmii core input line).
> +
> + clocks:
> + items:
> + - description: Clock for AXI register slave interface.
> + - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
> + - description: Ethernet reference clock, used by signal delay primitives
> + and transceivers.
> + - description: MGT reference clock (used by optional internal PCS/PMA PHY)
> +
> + clock-names:
> + items:
> + - const: s_axi_lite_clk
> + - const: axis_clk
> + - const: ref_clk
> + - const: mgt_clk
> +
> + axistream-connected:
> + type: object
> + description: Reference to another node which contains the resources
Reference? Meaning a phandle? Or this is a node because that's what
'type: object' says.
> + for the AXI DMA controller used by this device. If this is specified,
> + the DMA-related resources from that device (DMA registers and DMA
> + TX/RX interrupts) rather than this one will be used.
> +
> + mdio: true
type: object
> +
> + pcs-handle:
> + description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
> + modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
> + and "phy-handle" should point to an external PHY if exists.
> + $ref: /schemas/net/ethernet-controller.yaml#
The reference applies to nodes, but 'pcs-handle' is a property. It needs
to be at the top-level:
allOf:
- $ref: /schemas/net/ethernet-controller.yaml#
Rob
