From: Yassine Oudjana <y.oudjana@xxxxxxxxxxxxxx> These patches are part of a larger effort to support the MT6735 SoC family in mainline Linux. More patches (unsent or sent and pending review or revision) can be found here[1]. This series adds support for the main clock and reset controllers on the Mediatek MT6735 SoC: - apmixedsys (global PLLs) - topckgen (global divisors and muxes) - infracfg (gates and resets for internal components) - pericfg (gates and resets for peripherals) MT6735 has other more specialized clock/reset controllers, support for which is not included in this series: - mfgcfg (GPU) - imgsys (camera) - mmsys (display) - vdecsys (video decoder) - vencsys (video encoder) - audsys (audio) Changes since v2: - Add "CLK_" prefix to infracfg and pericfg clock definitions to avoid possible clashes with reset bindings. - Replace "_RST" suffix with "RST_" prefix to maintain consistency with clock bindings. - Use macros to define clocks. - Abandon mtk_clk_simple_probe/mtk_clk_simple_remove in favor of custom functions in apmixedsys and topckgen drivers for the time being. - Capitalize T in MediaTek in MODULE_DESCRIPTION. Changes since v1: - Rebase on some pending patches. - Move common clock improvements to a separate series. - Use mtk_clk_simple_probe/remove after making them support several clock types in said series. - Combine all 4 drivers into one patch, and use one Kconfig symbol for all following a conversation seen on a different series[2]. - Correct APLL2 registers in apmixedsys driver (were offset backwards by 0x4). - Make irtx clock name lower case to match the other clocks. [1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging [2] https://lore.kernel.org/linux-mediatek/CAGXv+5H4gF5GXzfk8mjkG4Kry8uCs1CQbKoViBuc9LC+XdHH=A@xxxxxxxxxxxxxx/ Yassine Oudjana (4): dt-bindings: clock: Add MediaTek MT6735 clock bindings dt-bindings: reset: Add MediaTek MT6735 reset bindings dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers .../arm/mediatek/mediatek,infracfg.yaml | 8 +- .../arm/mediatek/mediatek,pericfg.yaml | 1 + .../bindings/clock/mediatek,apmixedsys.yaml | 4 +- .../bindings/clock/mediatek,topckgen.yaml | 4 +- MAINTAINERS | 16 + drivers/clk/mediatek/Kconfig | 9 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 139 ++++++ drivers/clk/mediatek/clk-mt6735-infracfg.c | 78 +++ drivers/clk/mediatek/clk-mt6735-pericfg.c | 91 ++++ drivers/clk/mediatek/clk-mt6735-topckgen.c | 450 ++++++++++++++++++ .../clock/mediatek,mt6735-apmixedsys.h | 16 + .../clock/mediatek,mt6735-infracfg.h | 25 + .../clock/mediatek,mt6735-pericfg.h | 37 ++ .../clock/mediatek,mt6735-topckgen.h | 79 +++ .../reset/mediatek,mt6735-infracfg.h | 31 ++ .../reset/mediatek,mt6735-pericfg.h | 31 ++ 17 files changed, 1015 insertions(+), 5 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h -- 2.39.2
