Hi James & James, > On 13/11/14 12:58, Jude Abraham wrote: >>>> +/* timeout in seconds */ >>>> +#define PDC_WD_MIN_TIMEOUT 1 >>>> +#define PDC_WD_MAX_TIMEOUT 131072 >>>> +#define PDC_WD_DEFAULT_TIMEOUT 64 >>>> +#define PDC_WD_DEFAULT_PRETIMEOUT PDC_WD_MAX_TIMEOUT >>>> +#define MIN_TIMEOUT_SHIFT 14 /* Clock rate 32768Hz=2^(14+1)*/ >> >>> The input clock is not fixed at 32kHz. I believe it can be configured to run at a different rate. >> >> I think it is a 32 Khz fixed clock to the block. We are speaking to my hardware team for confirmation. >> We will address the review comment after receive feedback from my hardware team. > It should ideally be 32KHz, but that doesn't mean it will be guaranteed > to be. The input clock rate is still dependent on the SoC clock setup to > provide the clock, and that can usually be reconfigured i.e. from a > dedicated external oscillator on the board if provided (hopefully > providing the right frequency), or derived from a shared oscillator of > some other frequency. > For TZ1090 SoC with this IP block, powering down the rest of the SoC > happened to reset the low power clock configuration and it would switch > clock source to the main oscillator with a fixed divide, which certainly > wasn't 32khz most of the time. Each of the low power drivers had to then > take this into account in their configuration (img-ir for IR timings, > wdt to a lesser extent, and most importantly rtc so as not to lose time >or wake up at the wrong time!). Please suggest us any valid minimum and maximum clock rates for the Watchdog on Pistachio. Thanks and regards, Naidu.-- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
