Hi Luca,
On 23-02-22, Luca Ceresoli wrote:
> The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an
> NXPP SGTL5000 audio codec connected to I2S-0 (sai2).
>
> This requires to:
>
> * add the power supplies (always on)
> * enable sai2 with pinmuxes
> * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to
> IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate
>
> Signed-off-by: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx>
> ---
> .../dts/freescale/imx8mp-msc-sm2s-ep1.dts | 60 +++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> index 470ff8e31e32..894d9809f76d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts
> @@ -14,6 +14,57 @@ / {
> compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
> "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
> "fsl,imx8mp";
...
> +/* I2S-0 = sai2 */
> +&sai2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai2>;
> +
> + assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
> + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
> + assigned-clock-rates = <12288000>;
> +
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> };
Do you have some downstream patches for the sai interfaces? AFAIR Marek
worked on this but the patches are not mainlien yet.
Regards,
Marco
