On 22.02.2023 18:22, Vladimir Zapolskiy wrote:
> From: Thara Gopinath <thara.gopinath@xxxxxxxxx>
>
> Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
> etc. requires interconnect path between the engine and memory to be
> explicitly enabled and bandwidth set prior to any operations. Add support
> in the qce core to enable the interconnect path appropriately.
>
> Tested-by: Jordan Crouse <jorcrous@xxxxxxxxxx>
> Signed-off-by: Thara Gopinath <thara.gopinath@xxxxxxxxx>
> [Bhupesh: Make header file inclusion alphabetical and use devm_of_icc_get()]
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
> [vladimir: moved icc bandwidth setup closer to its acquisition]
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/crypto/qce/core.c | 16 +++++++++++++++-
> drivers/crypto/qce/core.h | 1 +
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 74deca4f96e0..0654b94cfb95 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -5,6 +5,7 @@
>
> #include <linux/clk.h>
> #include <linux/dma-mapping.h>
> +#include <linux/interconnect.h>
> #include <linux/interrupt.h>
> #include <linux/module.h>
> #include <linux/mod_devicetable.h>
> @@ -22,6 +23,8 @@
> #define QCE_MAJOR_VERSION5 0x05
> #define QCE_QUEUE_LENGTH 1
>
> +#define QCE_DEFAULT_MEM_BANDWIDTH 393600
> +
> static const struct qce_algo_ops *qce_ops[] = {
> #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
> &skcipher_ops,
> @@ -218,10 +221,18 @@ static int qce_crypto_probe(struct platform_device *pdev)
> if (IS_ERR(qce->bus))
> return PTR_ERR(qce->bus);
>
> - ret = clk_prepare_enable(qce->core);
> + qce->mem_path = devm_of_icc_get(qce->dev, "memory");
> + if (IS_ERR(qce->mem_path))
> + return PTR_ERR(qce->mem_path);
> +
> + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> if (ret)
> return ret;
>
> + ret = clk_prepare_enable(qce->core);
> + if (ret)
> + goto err_mem_path_disable;
> +
> ret = clk_prepare_enable(qce->iface);
> if (ret)
> goto err_clks_core;
> @@ -260,6 +271,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
> clk_disable_unprepare(qce->iface);
> err_clks_core:
> clk_disable_unprepare(qce->core);
> +err_mem_path_disable:
> + icc_set_bw(qce->mem_path, 0, 0);
> +
> return ret;
> }
>
> diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
> index 085774cdf641..228fcd69ec51 100644
> --- a/drivers/crypto/qce/core.h
> +++ b/drivers/crypto/qce/core.h
> @@ -35,6 +35,7 @@ struct qce_device {
> void __iomem *base;
> struct device *dev;
> struct clk *core, *iface, *bus;
> + struct icc_path *mem_path;
> struct qce_dma_data dma;
> int burst_size;
> unsigned int pipe_pair_id;
