On 21/02/2023 15:11, Xingyu Wu wrote:
> Add the PLL clock node for the Starfive JH7110 SoC and
> modify the SYSCRG node to add PLL clocks.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index b6612c53d0d2..0cb8d86ebce5 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -461,12 +461,16 @@ syscrg: clock-controller@13020000 {
> <&gmac1_rgmii_rxin>,
> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> - <&tdm_ext>, <&mclk_ext>;
> + <&tdm_ext>, <&mclk_ext>,
> + <&pllclk JH7110_CLK_PLL0_OUT>,
> + <&pllclk JH7110_CLK_PLL1_OUT>,
> + <&pllclk JH7110_CLK_PLL2_OUT>;
> clock-names = "osc", "gmac1_rmii_refin",
> "gmac1_rgmii_rxin",
> "i2stx_bclk_ext", "i2stx_lrck_ext",
> "i2srx_bclk_ext", "i2srx_lrck_ext",
> - "tdm_ext", "mclk_ext";
> + "tdm_ext", "mclk_ext",
> + "pll0_out", "pll1_out", "pll2_out";
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
> @@ -476,6 +480,13 @@ sys_syscon: syscon@13030000 {
> reg = <0x0 0x13030000 0x0 0x1000>;
> };
>
> + pllclk: pll-clock-controller {
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions). You should see here warnings of mixing non-MMIO nodes
in MMIO-bus.
Best regards,
Krzysztof
