From: Aswath Govindraju <a-govindraju@xxxxxx> The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx> Signed-off-by: Matt Ranostay <mranostay@xxxxxx> Link: https://lore.kernel.org/r/20221122101616.770050-6-mranostay@xxxxxx Signed-off-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> --- I had reviewed this patch in the v5 series [1]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. Links: [1] - https://lore.kernel.org/all/96058a13-4903-2b8c-8de2-f37fdfd3672b@xxxxxx/ .../dts/ti/k3-j721s2-common-proc-board.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 907f34ff22a5..fa38940fe6cd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; &wkup_pmx0 { @@ -323,6 +329,24 @@ }; }; +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + status = "okay"; + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- 2.17.1
