From: Aswath Govindraju <a-govindraju@xxxxxx> x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx> Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx> Signed-off-by: Matt Ranostay <mranostay@xxxxxx> Link: https://lore.kernel.org/r/20221122101616.770050-9-mranostay@xxxxxx Signed-off-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 76b420379645..b195f250891a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -386,6 +386,14 @@ }; }; +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- 2.17.1
