Currently, when booting on SparX-5 you will get the following error: [ 0.050132] Early cacheinfo failed, ret = -22 This is due to L2 cache node missing cache-level property to indicate its level, so populate it to let the kernel know its L2 cache. However, that alone is enough to get rid of the error, but then the following warnings appear: [ 0.050162] cacheinfo: Unable to detect cache hierarchy for CPU 0 [ 0.093256] cacheinfo: Unable to detect cache hierarchy for CPU 1 So, lets completely populate both the L1 and L2 cache info based off the SoC datasheet[1] and ARM A53 technical reference manual[2]. Now "lscpu -C" provides: NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SIZE L1d 32K 64K 4 Data 1 128 64 L1i 32K 64K 2 Instruction 1 256 64 L2 256K 256K 16 Unified 2 256 64 Tested on PCB134 (eMMC). [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/SparX-5_Family_L2L3_Enterprise_25G_Ethernet_Switches_Datasheet_00003823D.pdf [2] https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System/About-the-L1-memory-system?lang=en Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko <robert.marko@xxxxxxxxxx> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index a4fabacf5c2f7..950ba78bf73f3 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -41,6 +41,12 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set next-level-cache = <&L2_0>; }; cpu1: cpu@1 { @@ -48,10 +54,21 @@ cpu1: cpu@1 { device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; // 256KB(size)/64(line-size)=4096ways/16-way set + cache-level = <2>; }; }; -- 2.39.2
