On 20/02/23 8:15 pm, Andrew Davis wrote: > On 2/20/23 5:14 AM, Ravi Gunasekaran wrote: >> From: Aswath Govindraju <a-govindraju@xxxxxx> >> >> Add support for single instance of USB 3.0 controller in J721S2 SoC. >> >> Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx> >> Signed-off-by: Matt Ranostay <mranostay@xxxxxx> >> Link: https://lore.kernel.org/r/20221122101616.770050-2-mranostay@xxxxxx >> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx> >> --- >> I had reviewed this patch in the v5 series [1]. >> Since I'm taking over upstreaming this series, I removed the self >> Reviewed-by tag. >> >> Links: >> >> [1] - https://lore.kernel.org/all/134c28a0-2d49-549c-dc8d-0887d8fd29c3@xxxxxx/ >> >> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++ >> 1 file changed, 42 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi >> index 8915132efcc1..c0daa75116f9 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi >> @@ -26,6 +26,20 @@ >> }; >> }; >> + scm_conf: syscon@104000 { >> + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; >> + reg = <0x00 0x00104000 0x00 0x18000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x00 0x00 0x00104000 0x18000>; >> + >> + usb_serdes_mux: mux-controller@0 { >> + compatible = "mmio-mux"; >> + #mux-control-cells = <1>; >> + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ >> + }; >> + }; >> + >> gic500: interrupt-controller@1800000 { >> compatible = "arm,gic-v3"; >> #address-cells = <2>; >> @@ -745,6 +759,34 @@ >> }; >> }; >> + usbss0: cdns-usb@4104000 { > > Since this cannot be used without additional pinmux information in the > board level dtb files, this can be set disabled in this include file. Then > set back to "okay" where you add the pinmux. Same for the OSPI and PCIe patches. > > Andrew Sure. I will do so and post the next series. Ravi > >> + compatible = "ti,j721e-usb"; >> + reg = <0x00 0x04104000 0x00 0x100>; >> + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; >> + clock-names = "ref", "lpm"; >> + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ >> + assigned-clock-parents = <&k3_clks 360 17>; >> + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + dma-coherent; >> + >> + usb0: usb@6000000 { >> + compatible = "cdns,usb3"; >> + reg = <0x00 0x06000000 0x00 0x10000>, >> + <0x00 0x06010000 0x00 0x10000>, >> + <0x00 0x06020000 0x00 0x10000>; >> + reg-names = "otg", "xhci", "dev"; >> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "host", "peripheral", "otg"; >> + maximum-speed = "super-speed"; >> + dr_mode = "otg"; >> + }; >> + }; >> + >> main_mcan0: can@2701000 { >> compatible = "bosch,m_can"; >> reg = <0x00 0x02701000 0x00 0x200>,
