On 2/6/23 00:02, Michal Simek wrote:
On 2/6/23 00:02, Lars-Peter Clausen wrote:
The FIFO depth and maximum transfer length are Synthesis configuration
parameters of the Cadence I2C IP. Different SoCs will use different
values
for these parameters.
Currently the driver has the FIFO depth hardcoded to 16 and the maximum
transfer length to 255. Trying to use the driver with an IP instance
that
uses smaller values for these will work for short transfers. But longer
transfers will fail.
The maximum transfer length can easily be detected at runtime since the
unused MSBs of the transfer length register are hardwired to 0. Writing
0xff and then reading back the value will give the maximum transfer
length.
I think that these are pretty much two patches in one.
The first should target transfer length part and second fifo depth part.
Hm, I'm not sure it is worth separating this out. These two are very
tightly related, but I can split it.
/**
* cdns_i2c_probe - Platform registration call
* @pdev: Handle to the platform device structure
@@ -1242,6 +1274,7 @@ static int cdns_i2c_probe(struct
platform_device *pdev)
struct cdns_i2c *id;
int ret, irq;
const struct of_device_id *match;
+ u32 val;
id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
if (!id)
@@ -1317,6 +1350,12 @@ static int cdns_i2c_probe(struct
platform_device *pdev)
#endif
id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA |
CDNS_I2C_CR_MS;
+ val = CDNS_I2C_FIFO_DEPTH_DEFAULT;
you can remove val completely.
id->fifo_depth = CDNS_I2C_FIFO_DEPTH_DEFAULT;
But only if I make fifo_depth a u32.
...
